Answers Database

Timing Simulation shows XX's on the outputs of CORE Generator COREs containing ROM and/or R


Record #3663

Product Family:  Software

Product Line:  Coregen

Problem Title:
Timing Simulation shows XX's on the outputs of CORE Generator COREs
containing ROM and/or R



Problem Description:
Keywords:  xx, timing simulation

Urgency:  hot

General Description:
Outputs of CORE Generator COREs containing ROM and/or RAM may
be XX in simulation.


Solution 1:

X's may be seen on the outputs of CORE Generator modules
containing ROM or RAM when the function generator inputs are
forced to GND or VCC (Constant Coefficient Multipliers, FIR
Filters,for example).

The problem is caused by a bug in the Xilinx Mapper v1.4.

A Patch to the v1.4 Mapper is available on the Xilinx FTP site.

ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt14.zip





End of Record #3663