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Hardware Debugger: Readback verification disabled in XC5200 designs...


Record #3672

Product Family:  Software

Product Line:  FPGA Core

Problem Title:
Hardware Debugger: Readback verification disabled in XC5200 designs...


Problem Description:
Keywords: readback, 5200, failed, mismatch

Urgency: HOT

General Description:

Hardware Debugger states that the READBACK block is not present in the design; t
herefore, all readback verification and debugging features are disabled.  Howeve
r, the Readback module was indeed used in the design.

MAP M1.4 has CR 104301 filed for failing to route the DATA pin of the READBACK s
ymbol.	Until a patch is available the only workaround is to manually edit the .
ncd file in epic or return to the XACT6 S/W.


Solution 1:

To reroute the net connections in Epic Design Editor:

1. Invoke Epic on the routed ncd file.	Specify Read/Write Mode.
2. Select the Net attached to the RIP pin of the RDBK comp to get the <net_name>
.
3. Select the <net_name> in the Epic List.
4. Take note of all other connections to <net_name>.  Click on other attached pi
ns to get their <site.pin> name.
5. Click on Delete.  This will delete <net_name>.
6. Click on the .DATA pin of the RDBK comp as well as all other comp pins to be
connected to this net.
7. Click on Add.
8. Fill in the "Name:" field with the <net_name> of the net just deleted, and cl
ick on OK.
9.  The net should now be routed.  Save and exit.



End of Record #3672