Answers Database

Foundation Express, XC9500: Recommended synthesis and fitter options for CPLDs


Record #3705

Product Family:  Software

Product Line:  Synopsys

Problem Title:
Foundation Express, XC9500:  Recommended synthesis and fitter options
for CPLDs



Problem Description:
Keywords:  9500, cpld, fit, compile, synthesize, express, vhdl,
	   FPGA Express

Urgency:  Standard

Short Description:

Xilinx has been evaluating the Quality of Results of VHDL
designs targetted to XC9500 CPLDs which are compiled using
Foundation Express and FPGA Express.  Through our benchmarking,
we have established a set of "recommendations" for compiling
VHDL designs in the form of recommended synthesis and fitter
options.  This combination of settings has shown to provide
the best quality of results in terms of density and
performance for the largest number of our test designs.  This
is not to say that these settings will ALWAYS provide the best
results, but more often than not, we recommend at least trying
these when attempting to gain the best results.


Solution 1:

The following is a summary of our recommendations:

1.  In FPGA Express, use AREA optimization when synthesizing.
2.  In FPGA Express, use BINARY encoding for FSMs.
3.  In the CPLD Fitter (Design Manager), use the "Optimize for
    Speed" Implementation Template, and modify the PTERM
    Collapse limit to be 90.

Details for using these settings:

1.  AREA optimization in Express
================================
When creating an implementation in Express, select Optimize for
"Area" in the Create Implementation dialog box.

2.  BINARY encoding for FSMs
============================
From within FPGA Express, select Synthesis->Options->Project.
Under "Default FSM Encoding" select Binary.  Note that you must
re-analyze the design for this setting to take effect.	To
re-analyze, select Synthesis->Force Update.

3.  Fitter Optimize for Speed; Pterms=90
========================================
* From within the Design Manager, Implement the design.
* When the Implement dialog appears, hit the Options... button.
* From within the Options dialog, click on the pulldown menu
  under Implementation Program Option Templates, and select the
  one entitled Optimize Speed.
* Finally, hit Edit Template... and go to the Advanced
  Optimization tab.  Change the Collapsing Pterm Limit to 90.



End of Record #3705