Answers Database

A1.4/F1.4 Map - MAP introduces DRC problem: WARNING:x4kdr:82 - Blockcheck: The pin "F1"...


Record #3761

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
A1.4/F1.4 Map - MAP introduces DRC problem: WARNING:x4kdr:82 -
Blockcheck: The pin "F1"...



Problem Description:
Map introduces DRC problem by configuring a CLB for external
feed back but failing to define the external signal. This
results in warnings about configured CLB pins that have no
signal attached:

WARNING:x4kdr:82 - Blockcheck: The pin "F1" on comp (mapped
physical logic cell) "U18/PWMPHC0_D" is configured to be used
but has no signal attached to it.




Solution 1:

This problem is fixed in the latest M1.4 Core Tools Patch
available on the Xilinx Download Area:

ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt14.zip




End of Record #3761