Answers Database

V1.4.0 COREGEN: After FULL indicator goes high, FIFO output changes to the first value written before READ ENABLE goes active.


Record #3791

Product Family:  Software

Product Line:  Coregen

Problem Title:
V1.4.0 COREGEN: After FULL indicator goes high, FIFO output changes to
the first value written before READ ENABLE goes active.



Problem Description:
Keywords:  coregen, fifo, full

Urgency:  standard

General Description:
After all memory locations in the COREGen FIFO are filled and
the  FULL status output goes High, if WE is still asserted on
the next clock cycle, the FIFO output displays the value that
was written to it at the first memory location, even though
the RE (READ ENABLE) input was never asserted.


Solution 1:


The CORE Generator RAM-based FIFO was designed to minimize the
number of clock cycles required to write valid data to, or
read valid data out of, this buffer.  Internally there is a
Write Counter that points to the address of the next writable
address in the buffer, and a Read Counter, which points to the
next address location to be read.

In a Single Port RAM-based FIFO, a mux selects either the
Write Counter or the Read Counter to provide the address to
the memory.  The RE input acts as the mux select control
signal.  The WRITE Counter always points to the next memory
location to be written to, to allow the fastest possible WRITE
operation.

Once the last FIFO memory location has been written to, the
FIFO is now FULL, and the WRITE Counter cycles back to the
first memory location.	The value stored at this location
appears at the output of the FIFO even though RE is not
asserted, because the WRITE Counter is providing the
address to the memory (this is because RE is not asserted).
If WE is still enabled on the next clock cycle, the current
contents of the next location will appear at the FIFO output.
Of course, the information at this location will not be
overwritten, because the FIFO is now FULL.

Since RE has not been asserted, you should not care what the
FIFO output is at that point.  If you subsequently assert RE,
you should still see the same value at the output.




End of Record #3791