Answers Database

Exemplar Leonardo 4.x: How to instantiate READBACK using RDBK and RDCLK


Record #3792

Product Family:  Software

Product Line:  Exemplar

Problem Title:
Exemplar Leonardo 4.x:  How to instantiate READBACK using RDBK and RDCLK


Problem Description:
Keywords:  Leonardo, Exemplar, VHDL, verilog, readback, rdbk, rdclk

Urgency:  Standard

General Description:  How can I instantiate the READBACK symbol
in Leonardo using VHDL or verilog?


Solution 1:

--4K devices, VHDL, Readback using CCLK:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity use_readback is
      port (trig : in std_logic;
	    rip : out std_logic;
	    data: out std_logic;
	    CLK, D_IN: in std_logic;
	    Q: out std_logic);
end use_readback;

architecture xilinx of use_readback is

component RDBK
	port (TRIG: in std_logic;
		DATA: out std_logic;
		RIP: out std_logic);
end component;

begin

U1: RDBK port map (TRIG => trig, DATA => data, RIP => rip);

-- Sample User Code
My_D_Reg: process (CLK, D_IN)
    begin
	if (CLK'event and CLK='1') then
	    Q <= D_IN;
	end if;
end process; -- End My_D_Reg

end xilinx;



Solution 2:

--4K devices, VHDL, Readback using USER Clock:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity use_readback is
      port (trig : in std_logic;
	    rip : out std_logic;
	    data: out std_logic;
	    CLK, D_IN: in std_logic;
	    READ_CLK : in std_logic;
	    Q: out std_logic);
end use_readback;

architecture xilinx of use_readback is

component RDBK
	port (TRIG: in std_logic;
		DATA: out std_logic;
		RIP: out std_logic);
end component;

component RDCLK
	port (I : in std_logic);
end component;

begin

U1: RDBK port map (TRIG => trig, DATA => data, RIP => rip);
U2: RDCLK port map ( I => READ_CLK);

-- Sample User Code
My_D_Reg: process (CLK, D_IN)
    begin
	if (CLK'event and CLK='1') then
	    Q <= D_IN;
	end if;
end process; -- End My_D_Reg

end xilinx;



Solution 3:

// 4K Devices, Verilog, Readback using CCLK

module use_readback (CLK, TRIG, DATA, RIP, d_in, d_out);
  input  CLK, TRIG, d_in;
  output DATA, RIP, d_out;

  reg d_out;

  RDBK U1 (.TRIG(TRIG), .DATA(DATA), .RIP(RIP));

  always @ (posedge CLK)
       d_out = d_in;

endmodule

module RDBK(TRIG, DATA, RIP);
  input  TRIG;
  output DATA, RIP;
endmodule




Solution 4:

// 4K devices, Verilog, Readback using USER Clock

module readback_example (READ_CLK, CLK, TRIG, DATA, RIP, d_in, d_out);
  input  READ_CLK, CLK, TRIG, d_in;
  output DATA, RIP, d_out;

  reg d_out;

  RDCLK U1 (.I(READ_CLK));

  RDBK U2 (.TRIG(TRIG), .DATA(DATA), .RIP(RIP));

  //Sample User Code
  always @(posedge CLK)
     d_out = d_in

endmodule

module RDCLK (I);
  input I;
endmodule

module RDBK(TRIG, DATA, RIP);
  input  TRIG;
  output DATA, RIP;
endmodule




End of Record #3792