Answers Database

M1.4 CPLD - Timing violation: Slow simulation model produced with the "Use Local Macrocell Feedback" switch


Record #3802

Product Family:  Software

Product Line:  CPLD Implementation

Problem Title:
M1.4 CPLD - Timing violation: Slow simulation model produced with the
"Use Local Macrocell Feedback" switch



Problem Description:
Keywords:  Cpld, M1.4, hold, time, simulation, macrocell, feedback, violation

Urgency:   Standard


Simulation model created slower than the correct model.

Hold time errors reported when running design at slower clock
rate than reported by the Timing Analyzer.  The reported design should have
run at 100Mhz, but gave timing violations at 20Mhz.
The design simulated properly when the "Use Macrocell Feedback" switch
is not being used.  The patch referred to below solves this for M1.4.



Solution 1:

This problem is fixed in the latest M1.4 CPLD Tools Update
available on the Xilinx Download Area:

ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/cpld_sol9_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/cpld_sun9_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/cpld_hp9_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/cpld_nt9_m14.zip

These update files also include the changes from previous cpld updates.

All zip files are created using WinZip. To obtain this utility,
access WinZip's web site at http://www.winzip.com



End of Record #3802