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A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:908:1.69 - No pins of NC_SIGNAL ...


Record #3810

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
A1.4/F1.4 Map - FATAL_ERROR:baste:bastetspec.c:908:1.69 - No pins of
NC_SIGNAL ...



Problem Description:
An environment variable (XIL_MAP_TOLERATE_TIG_ERROR) has been
added that changes certain timespec related fatal errors to
warnings. The errors ocurr when the correlation between the logical timespec con
straint and the physical implementation is lost during mapping. Use of the envir
onment variable caused
the timespec to be lost, but allows map to continue. Many
of these cases have to do with lost TIGs, so the impact of
the lost timespec is that a path is over constrained.


Solution 1:

This new feature can be accessed by installing the latest M1.4 Core Tools Update
 available on the Xilinx Download Area:

ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt14.zip

Setting the environment variable:
setenv XIL_MAP_TOLERATE_TIG_ERROR (work stations)
set XIL_MAP_TOLERATE_TIG_ERROR = TRUE (PCs)



End of Record #3810