Answers Database

V1.4.0 COREGEN: Tips on simulating the SDA FIR filter


Record #3846

Product Family:  Software

Product Line:  Coregen

Problem Title:
V1.4.0 COREGEN:	Tips on simulating the SDA FIR filter


Problem Description:
Keywords: Serial Distributed Arithmetic FIR filter, simulation

Urgency: standard

General Description:
There are a number of things to note when simulating the
SDA FIR Filter core produced by the CORE Generator.


Solution 1:


COREGEN v1.4.1:
---------------
1. The latest version of this core (v1.14 or later) can be
found on the Xilinx CORELINX web site,

  http://www.xilinx.com/products/logicore/coregen/corelinx.htm


To simulate the filter:

2. You should assert global reset for at least one clock
cycle to initialize the entire design.	This is a gneral rule
for any design that contains flip-flops and/or latches.

3. When RFD goes high, you can then assert the first data.
The input data and the ND input must both be stable for some
period of time before the data is clocked in on the next
rising clock edge.  Asserting both ND and data shortly after
the falling edge of the clock should ensure that this
requirement is met.  ND ("New Data") can be asserted (driven
high) on the same falling clock edge as the data, and should
be asserted for one clock cycle.

4. ND should NEVER be asserted when RFD is low.
If this ever occurs, the filter's operation becomes undefined
for a number of clock cycles.  During this period, the
behavioral model and the actual filter behavior will not
match.

The output on the RSLT port will be valid when RDY goes high.


5. Due to a bug (CR 103333) with trimming of unused outputs by
COREGen, you should maintain the maximum output bus width
possible for the number of taps you specify (do not select
anything smaller than the maximum value displayed in the
GUI for output bus width).



End of Record #3846