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V1.4.0 COREGEN, FPGA EXPRESS: How to generate Foundation functional simulation files for a VHDL design


Record #3863

Problem Title:
V1.4.0 COREGEN, FPGA EXPRESS:  How to generate Foundation functional
simulation files for a VHDL design



Problem Description:
Keywords: coregen, foundation, simulation, vhdl

Urgency: standard

General Description:
Simulating a VHDL design with the Foundation
simulator requires that a Foundation simulation netlist (.ALR)
file be generated for the design.




Solution 1:

Currently with the CORE Generator software, if the user is
using a top level VHDL file in Foundation, the only way
you can generate the .ALR for a COREGen module is to select
"Foundation Schematic Symbol" as one of your output
formats when he sets the Output Options.

Details on the Foundation VHDL flow can be found in the
online CORE Generator User Guide.



End of Record #3863