Answers Database

A1.4/F1.4 Map - Map connects wrong LUT output to FFY D input


Record #3875

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
A1.4/F1.4 Map - Map connects wrong LUT output to FFY D input


Problem Description:
A case has been seen where map corrupted the logic
of a CLB by connecting the wrong LUT output to the
D-input of a Flop.

A patch is available for this problem.


Solution 1:

This problem is fixed in the latest M1.4 Core Tools Update
available on the Xilinx Download Area:

ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp14_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt14.zip



End of Record #3875