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M1 TRCE : How does trce list the number of timing errors?


Record #3888

Problem Title:
M1 TRCE : How does trce list the number of timing errors?


Problem Description:
Keywords: trce

Urgency: Standard

General Description:

How does trce list the number of timing errors?

Then notice that, of the 512 paths analyzed, 81 of them (*not* 4)
actually have timing errors (negative slack)


Solution 1:

As per the M1.4 Trce Product Functional Specification, the number of
timing errors listed in the timint report now reflects the number
of path endpoints which fail to meet the timing specification (rather
than the total number of paths to these path endpoints).

Trce used to be path-based; it would enumerate all paths for each
constraint and count the number of paths that failed the timespec.
With the advent of non-enumerative timing analysis (i.e. KPATHS), Trce
no longer analyzes all of the paths in the design.  The positive result
of this is faster runtimes, but the negative side-effect was that Xilinx
can no longer determine (quickly) the number of paths that failed a
timespec.

The method for calculating the number of timing errors now counts
the number of path endpoints (registers, rams, pads) that failed
to meet the timespec. This was done for both the old depth-first
search method (DFS) and the new kpaths method for consistency.



End of Record #3888