Answers Database

Verilog: Timing simulation: An X_FF waveform does not look correct and may be mistaken for a latch


Record #3930

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
Verilog: Timing simulation: An X_FF waveform does not look correct and
may be mistaken for a latch



Problem Description:
Keywords: verilog, X_FF

Urgency: Standard

General Description:  An X_FF instance may not appear to work properly
during timing simulation.


Solution 1:


The waveform of an X_FF in timing simulation may look not appear
to be operating properly due to fact that the clock delay is modeled at
the pin of the X_FF model since the Verilog Language does not allow
annotation of signal delays to wire data types.  If the
data of the flip flop is toggled after a rising edge of the
clock and the data path delay is smaller then the clock delay,
the waveform may not look as expected and may resemble a latch
operation.

To make sure that the flip flop is behaving correctly, you
may want to check the SDF file for this particular X_FF and
take in consideration that the actual clock that the X_FF
sees is delayed by the number reported in the SDF file.

For example,
...
   (CELLTYPE "X_FF")
    (INSTANCE a1_u13_a3_u1_dat_out\<0\>)
    (DELAY
      (ABSOLUTE
	(PORT IN  (0:0:0) (0:0:0))
	(PORT CLK  (6107:6107:6107) (6107:6107:6107))
...

The delay on the clock pin is 6.1 ns.





End of Record #3930