Answers Database

M1.4 Fitter/Hitop - Incorrect logic generated.


Record #4048

Product Family:  Software

Product Line:  CPLD Implementation

Problem Title:
M1.4 Fitter/Hitop - Incorrect logic generated.


Problem Description:
Customer doing an VHDL design with the following equations:

RST <= not RST_N;

RST_N <= reset_in_n and watchdog_rst_n;

In the functional simulation, the logic is correct.

After running the design through the core tools the fitter report shows the equa
tion to be:

/RST = reset_in_n * watchdog_rst_n

/RST_N = reset_in_n * watchdog_rst_n

The signal is incorrect and the customer verified it by doing a timing simulatio
n.  It appears that the fitter is inverting the signal twice.

Please see the readme.txt for command lines used.


Solution 1:

This problem has been corrected in the following CPLD Tools Update:

ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/cpld_sol9_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/cpld_sun9_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/cpld_hp9_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/cpld_nt9_m14.zip

These update files also include the changes from previous cpld updates.

All zip files are created using WinZip. To obtain this utility,
access WinZip's web site at http://www.winzip.com



End of Record #4048