Answers Database

M1.4: WARNING:x4edr:21 - Blockcheck: CLB "frfi3_alism_fiCtr_upDown" is configured to use the G LUT as RAM, but the D1 and WE lines use the same pin, wh ich will likely cause a D->WE setup violation.


Record #4072

Product Family:  Software

Product Line:  FPGA Implementation

Problem Title:
M1.4: WARNING:x4edr:21 - Blockcheck: CLB "frfi3_alism_fiCtr_upDown" is
configured to   use the G LUT as RAM, but the D1 and WE lines use the same pin,
wh
ich will   likely cause a D->WE setup violation.



Problem Description:
Keywords: Blockcheck, ram, we, d1, configure

Urgency : Hot

General Description:
Map give the following warning:
WARNING:x4edr:21 - Blockcheck: CLB "frfi3_alism_fiCtr_upDown" is configured to
   use the G LUT as RAM, but the D1 and WE lines use the same pin, which will
   likely cause a D->WE setup violation.




Solution 1:

This is an incorrect warning. The SR mux is driving WE. The
same signal drives the H-LUT thru the H1 mux. Because the H1
mux also drives D1, drc warns about the setup violation.
The drc check doesn't realize that the D1 pin is going to the
H1 input of the HLUT not the D1 input of the RAM MODE block.
This is an incorrect warning because the DPRAM configuration
does not use D1.

This has been fixed in M1.5.

For now, the workaround is to use -d option in bitgen to
ignore the DRC error checking.



End of Record #4072