Answers Database

M1.5 9500/XL FITTER/HITOP: PROHIBIT property does not exclude pins from "Programmable Ground Pins" option


Record #4100

Product Family:  Software

Product Line:  CPLD Implementation

Problem Title:
M1.5 9500/XL FITTER/HITOP: PROHIBIT property does not exclude pins from
"Programmable Ground Pins" option



Problem Description:
Keywords:  CPLD, Fitter, 9500, HITOP, PROHIBIT, property, programmable, ground

Urgency:   Standard

General Description:
The PROHIBIT property can be used to reserve specific device pins so
they remain unused by the CPLD fitter. However, if you enable the
implementation option "Create Programmable Ground Pins on
Unused I/O", all unused pins, including those listed in the
PROHIBIT property, are connected to the device's ground network.

A software patch will be provided that will leave all PROHIBIT
pins undriven (floating) when the Programmable Ground Pins option
is enabled. Please check the technical support area of the Xilinx web-
site (www.xilinx.com) for the availability of a Version 1.5 CPLD fitter
patch that you can download to fix this problem. This patch will
allow you to connect PROHIBIT pins to live traces on your board in
anticipation of future CPLD design iterations, even if you use the
Programmable Ground Pins option.


Solution 1:

Workaround:

Until the CPLD fitter patch becomes available, you can
work around this problem by creating dummy input and
output pins in your design, instead of using the PROHIBIT
property to reserve those pins.

To create a dummy output pin that always remains in the
high-Z state, implement a flip-flop with a constant zero
as its clock and/or data input. The flip-flop will power-up
and remain in the zero state. Then use the flop output
to drive both the data and output-enable lines of one or more
3-state output buffers (OBUFE).

To create dummy input pins, combine all associated input
buffers (IBUF) into an AND-gate.  Then use the AND-gate
output to drive the asynchronous clear input of the same
flip-flop used to create the dummy output pins.

CR 104919.



Solution 2:

A more convenient way to create a dummy output pin that remains at High-Z is to
instantiate a 3-state output buffer (like OBUFE) and tie its output enable pin (
E) to ground. In VHDL, you could use the following equivalent solution:
zero signal: bit :='0'; ...
dummy_pin <= 'Z' when zero = '0' else '0';



End of Record #4100