Answers Database

M1.5 9500XL Fitter/Library: Clock-enable p-term not used for FDPE in Cadence and Mentor schematics.


Record #4173

Product Family:  Software

Product Line:  Merged Core

Problem Title:
M1.5 9500XL Fitter/Library: Clock-enable p-term not used for FDPE in
Cadence and Mentor schematics.



Problem Description:
Keywords:  CPLD, Fitter, 9500, 9500XL, Mentor, Cadence, Concept, FDPE, CE

Urgency:   Standard

General Description:
In M1.5, the symbols FDCE and FDPE in the 9500/XL schematic libraries are suppos
ed to be primitives and cause the 9500XL fitter to use the macrocell clock-enabl
e p-term to implement the CE-input. In Cadence (Concept and Verilog) and Mentor
libraries, FDPE is incorrectly configured as a macro with its CE input implement
ed as gate logic on the flip-flop D-input path.


Solution 1:

Workaround:
To implement a flip-flop with async preset and clock-enable using the 9500XL clo
ck-enable p-term, use a FDCE primitive in negative logic form instead of FDPE. I
nvert the D-input and Q-output of the FDCE, and connect your async preset to its
 CLR input. Also apply the INIT property to the FDCE indicating the opposite pow
er-on state that you would normally specify for a FDPE.



End of Record #4173