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TABLE 1B

Hermetic Package / Product Qualification Requirements Per Die Size (Commercial)

TEST SEQ
TEST DESCRIPTION
 ACC#/SAMPLE SIZE PER DIE SIZE CATEGORY  
(Note #2)
NEW PKG FAMILY
NEW PKG QUALIFIED FAMILY
LEAD FRAME
DIE ATTACH
WIRE BOND
TYPE OF SEAL
LEAD FINISH
NEW CAVITY SIZE
NEW DEVICE
NEW FAB PROCESS
FULL QUAL
   
(Note #1)
  
CAT.1
CAT.2
CAT.3
(Note #3)
(Note #4)
          
(Note #5)
(Note #6)
  
(Note #9)
B1
   Solder Heat Test (Optional)  
0/15
0/15
0/15
X
X
      
X
  
X
    
X
B2
*
 Resist. To Solvents
(Note #7)
0/3
0/3
0/3
X
          
X
      
X
B3
*
 Solderability Test
(Note #7)
0/3
0/3
0/3
X
  
X
      
X
      
X
B4
*
 Die Shear / Stud Pull
(Note #7)
0/5
0/5
0/5
X
X
  
X
          
X
X
B5
*
 Bond Pull
(Note #7)
0/5
0/5
0/5
X
X
X
  
X
        
X
X
B6
*
 External Visual
(Note #7)
0/25
0/25
0/25
X
X
X
    
X
  
X
    
X
B7
   Internal Visual
(Note #7)
0/5
0/5
0/5
X
X
X
X
X
      
X
X
X
B12
*
 Lead Material/Plating Thickness  
0/3
0/3
0/3
X
  
X
      
X
      
X
B13
   Process Cross Section  
2
2
2
                  
X
X
C1-A
   High Temp Life Test  
0/76
0/32
0/22
                
X
X
X
C1-B
   Low Temp Life Test
(Note #7)
0/22
0/22
0/22
                  
X
X
C3
   ESD (HBM)
(Note #8)
0/3 (9)
0/3 (9)
0/3 (6)
                
X
  
X
C4
   High Temp Storage (Optional)  
0/77
0/32
0/22
                  
X
X
D1
*
 Phy. Dimension  
0/5
0/5
0/5
X
X
        
X
X
    
X
D2
*
 Lead Integrity  
0/3
0/3
0/3
X
X
X
      
X
      
X
D3
   Thermal Shock + Temp Cycle + Moisture Resistance
0/15
0/15
0/15
X
X
X
X
X
X
X
X
    
X
D4
   Mech. Shock + Vibration + Constant Acceleration
0/15
0/15
0/15
X
X
X
X
X
X
  
X
    
X
D5
*
 Salt Atmosphere  
0/15
0/15
0/15
X
X
X
      
X
      
X
D6
*
 Internal Vapor Content
(Note #7)
0/3
0/3
0/3
X
X
  
X
  
X
  
X
    
X
D7
*
 Adhesion of L/Finish (Optional)  
0/3
0/3
0/3
X
X
X
      
X
      
X
D8
*
 Lid Torque  
0/5
0/5
0/5
X
X
      
X
  
X
    
X
D9
   Temp Cycle  
0/76
0/32
0/22
X
X
  
X
X
X
  
X
X
X
X
E1
   Electrical Test & Datalog  
0/30
0/20
0/10
                
X
X
X
E2
   Electrical Characterization  
0/30
0/30
0/30
                
X
X
X
E3
   T.D.D.B.
(Note #7)
-
-
-
                  
X
X
E4
   Latch-Up  
0/10
0/10
0/4
                
X
  
X
E5
   Electromigration
(Note #7)
-
-
-
                  
X
X
E6
   Photosensitivity (Optional)  
0/11
0/11
0/11
                
X
X
X
E7
   Data Retention Bake (EPLD & EPROM)  
0/45
0/22
0/15
                
X
X
X
E8
   Input/Output Capacitance  
0/5
0/5
0/3
                
X
  
X
E9
   Power Cycling  
0/76
0/32
0/22
                
X
X
X
Qty required per lot
Electrically good
126/82/72
126/82/72
35
111/67/57
111/67/57
121/77/67
15
121/77/67
373/208/150
449/240/183
518/325/241
Electrical Rejects
81
69
57
8
5
33
35
38
0
10
78
Total Units Required 
207/163/153
195/151/141
92
119/75/65
116/72/62
154/110/100
50
159/115/105
373/208/150
449/240/183
596/403/319
 

Notes:
1)
 Refer to Table #2 for test method and stress conditions.
2)
 Category 1 die size is <.571" x .643"; Category 2 die size is <.764" x .864"; Category 3 die size is >/=.764" x .864". Refer to Section 8.1.
3)
 Qualification of a new assembly plant, or, any new package which has not been qualified in the qualified assembly facility.
4)
 Package Type - A package with a unique case outline, configuration, material, piece parts and assembly processes.
5)
 Applicable to new piece parts or leadframe where the cavity size is larger than the largest cavity size for the same package.
6)
 For new mask from same device family, HTOL may or may not be required; ESD, LU, CAP and CHARDATA are required.
7)
 In process monitor data may be used to satisfy this requirement; for Qual data, data from Assy lot traveller may be used.
8)
 Acceptance criteria is 0/3, however 9 devices are required for ESD design characterization.
9)
 A full qualification is for process, assembly site and package.
* 
 Electrical rejects can be used as test sample.
 
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