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PeakVHDL

Accolade Design Automation's mission is to provide high quality, affordable tools for electronic design automation, with a particular focus on hardware description languages and FPGA applications. Accolade Design Automation products, which include the PeakVHDL simulator and PeakVHDL FPGA synthesis options, offer well-proven and reliable methods for design capture, analysis, and implementation.

All of our products include comprehensive, synthesis-oriented examples and training aids, tutorial-oriented documentation, VHDL Wizards, and other ease-of-use features. PeakVHDL and its PeakSynthesis options have been specifically designed for FPGA users, and have the power to meet the needs of Xilinx users in all application areas.

Product Highlights

• VHDL synthesis optimized for FPGA architectures, including all Xilinx families
• Direct generation of FPGA netlists, including module/primitive inference
• Automatic generation of I/O buffers (IOBs) for top-level modules
• VHDL simulation integrated tightly with synthesis for fast design iteration
• Support for multiple FPGA vendors in a single package
• Optional libraries add simulation support for FPGA macros
• Synthesis option uses the underlying technology, Metamor

Xilinx-Specific Highlights

• Generation (inference) of X-BLOX primitives built-in
• Direct generation of XNF netlists
• Includes support for foreign macrocells, such as Xilinx library elements, within the VHDL design description
• Xilinx simulation library option adds simulation support for Xilinx library elements

Design Flow

The PeakVHDL design environment creates optimized, FPGA-specific netlists from VHDL design descriptions. Using PeakVHDL simulation, VHDL test benches can be written to verify a design prior to synthesis. Netlists generated by PeakVHDL's synthesis option are ready for use in the Xilinx XACT environment.