Logic Synthesis for Verilog & VHDL Hardware Description Languages
Asyn^tm synthesizes behavioral Verilog or VHDL into gate-level netlists. The process involves language synthesis, followed by Boolean optimization and technology mapping to the target technology library . The entire process is area (cost) and/or timing (performance) driven. Asyn^tm supports a hierarchical design methodology. HDL models can be hierarchical, with one module calling the other, forming any depth of design hierarchy. Asynä also lets you completely or selectively preserve or flatten design hierarchy in any arbitrary manner. Asyn is the price-performance synthesis leader in the industry, with advanced technology available on both Unix and WindowsNT.

Product Highlights

• Fully compatible with the leading synthesis language subset
• Optimize for area and timing
• Large capacity (150K+ gates) with very fast run times
• Optional HDL signal name preservation
• Mixed-level input (behavioral and structural)
• Preserve or flatten design hierarchy entirely or selectively
• Built-in timing analyzer
• Available on Unix workstations and PC/Windows (NT, 95)

Xilinx Specific Highlights

• Optimization of CLB and IOB structures for all Xilinx FPGAs
• Backannotation of post-layout timing - directly from XACT using XNF
• Automatic PAD insertion and mapping to X-BLOX functions
• Forward passing of constraints to XACT
• XNF to Verilog or VHDL netlist creation for pre- or post-layout simulation
• Supports XILINX FPGAs (XC3000, XC4000, XC5000)

Design Flow

1. Describe your design in Verilog or VHDL
2. Perform functional simulation of the design
3. Use Asyn to synthesize your HDL into an optimized XNF netlist
4. Run XACT on XNF for Xilinx place and route
5. Backannotate post-layout XNF to Asyn for full timing report on critical paths

Gatran^©

Mixed HDL & Gate Design Optimization & Migration
In an age where product life cycles are shrinking and the requirement to have twice the complexity in the half time increases, design re-use is more important than ever. Gatran migrates your ASIC or FPGA design to a new target FPGA. Leverage your existing work by intelligently migrating previous designs or selected hierarchies. User controlled net name preservation and hierarchical optimization gets you the best possible results in the shortest period of time. By maintaining the original net names, existing simulation and test vectors can be re-used, speeding the final validation process. All ACEO tools work from the same software core, same libraries, and same consistent GUI. This provides a highly integrated solution to support your design needs, whether you start from HDL, mixed HDL and gates, or an existing synthesized design.

Product Highlights

• Design re-use leverages existing work
• Complete multi-directional intelligent technology migration
• Original simulation and test vectors can be re-used
• Selectable migration methods, at any level of design hierarchy
• Net-Name Preservation (NNP)
• Timing or area driven netlist optimization
• User controlled hierarchical optimization
• Hierarchy Browser user interface facilitates hierarchy re-structuring and hierarchical constraint setting
• Available on Unix workstations and PC/Windows (NT, 95)

Xilinx Specific Highlights

• Synthesize non-implementable logic due to technology differences (e.g. Handles sequential logic for Xilinx FPGAs)
• Handle both asynchronous and synchronous designs
• Merge multiple chips and technologies into one single design
• Read timing back-annotation files from XNF file · Supports XILINX FPGAs (XC3000, XC4000, XC5000)

Design Flow

1. Start with a structural netlist in EDIF, Verilog, VHDL or XNF
2. Choose target library
3. Select optimization parameters
4. Migrate

SoftWire^©

Multi-FPGA Partitioning and Rapid ASIC Prototyping Software
For large designs that exceed the usable gate count of a single FPGA, the design must be partitioned. Multi-FPGA design partitioning is a tedious, difficult, yet important task because the result greatly affects the performance and cost of the final product. SoftWire automates the partitioning process and is driven by performance and cost considerations. Built-in FPGA architecture-specific technology-mapping further enhances FPGA utilization and design efficiency.

SoftWire starts with automatic mapping of your synthesized design to FPGAs. To insure partitioning accuracy and the most aggressive results for Xilinx-based prototyping, the design is mapped to Xilinx CLBs instead of gates. Logic that cannot be directly implemented by the FPGA technology (such as certain FFs) is automatically synthesized. Net names can be preserved to any extent you desire, from 0% (unconstrained optimization), to as-much-as-possible (mapping only), to 100% preservation. You can also explicitly specify nets to be preserved or nets to be exposed at the FPGA device pins. The objective is to make mapping efficient and automatic.

Product Highlights

• Automatic, incremental, or mixed manual partitioning
• Timing analysis/adjustment throughout the entire process
• Mapping of external components (memory, mega-cells...)
• Handling of black-box modules; no netlist cut-and-paste
• User-controllable FPGA utilization ratios for logic modules and I/O pins
• Controllable pre-assignment of design modules to specific FPGAs or FPGA I/O pins
• Optional functional hierarchy-based partitioning
• Built-in hierarchical timing analyzer with board-level delay considered
• Engineering change order support with incremental partitioning
• Available on Unix workstations and PC/Windows (NT, 95)

Xilinx Specific Highlights

• Accurate Xilinx architecture partitioning
• Automatic mapping to CLB
• Clock tree extracted and handled separately from the rest of the logic
• Hierarchy can be selectively preserved or flattened
• Emulation frequency estimation (post-layout timing XNF backannotation)

Design Flow

1. Start with a structural netlist in EDIF, Verilog, VHDL or XNF
2. Choose target library or libraries
3. Select partitioning parameters
4. Partition