Acugen's ATGEN software automatically generates high coverage functional test vectors for Xilinx FPGA and EPLD devices. ATGEN software uses a variety of algorithms to produce the most comprehensive test available in today's market.

When ATGEN vectors are applied using standard ATE equipment, common manufacturing defects, such as shorts, opens, mis-programs and mis-inserted parts, are readily detected. ATGEN software is equally effective for programmable once, reprogrammable, and HardWire Gate Array devices.

Acugen Software offers a variety of system configurations to meet the needs of all customers, from simple screening to functional device verification. Our in-depth customer support organization and our 60-day money-back guarantee policy ensure our customers' success in meeting all of their testing needs.

Product Highlights

• Output for a complete line of translators for commercial ATE equipment (GenRad, Hewlett-Packard, Schlumberger, Teradyne, and others)
• Operates on PC, Open VMS VAX, SUN-4 OS, HP-9000 Series 700/HP- UX, DEC Alpha OSF, and Windows NT
• Easy-to-use, fully automatic test generation
• Provides functional, DC, and AC device test generation
• Guarantees the highest fault coverage on large designs

Xilinx-Specific Highlights

• Works with all Xilinx implementations, including HardWire Gate Array devices
• Especially useful in testing for fabrication defects in HardWire (mask programmed) devices
• Provides up-to-date support of Xilinx macros and devices
• Offers a variety of test choices, including a synthetic test approach where original configuration is not available at board test
• Ensures high coverage even in difficult situations with complex designs
• Tools to help program LCA devices from the tester
• Helps check for errors introduced when synthesizing a high level design

Design Flow

Acugen's AALCA product allows Xilinx users two useful approaches for the creation of board level tests: synthetic and netlist.

The synthetic approach exploits reconfigurability to substitute a simple combinatorial design with equivalent I/O pin declarations for a difficult-to-test netlist. This simplified netlist is created by supplying AALCA a place and routed .LCA file that AALCA scans for all required information. The tester I/O can be used to load the derived design into the device via the handshaking modes available on the chip. Some users prefer to simply create a new PROM and add it to the test fixture in such a way as to allow the Xilinx device to read the new netlist on power up. This type of test is short, easy, and can be expected to test 100% of the device pinouts. Most of the common assembly defects are caught by this type of test.

The netlist approach generates a test for the designer's netlist. For non-reconfigurable or HardWire Gate Array devices, using the netlist approach is the only practical method of generating a test. This method is also an option for reconfigurable devices. For this option AALCA reads a unit delay, gate-level simulation model style .NF file created by running the Xilinx lca2xnf utility on the placed and routed designname.lca file. The tests created by this process reflect the actual design intent. This can extend the scope of the test to detect a wider spectrum of problems. For example, such a test could detect when the wrong masked part, or the wrong revision of a design appears in a socket.