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HDS and SPW
Alta Group
of Cadence Design Systems, Inc.
555 Mathilda Avenue
Sunnyvale, CA 94086 U.S.A.
Tel: 1-408-733-1595
Fax: 1-408-523-4601
http://www.cadence.com/alta/
Alta Group has products and services for communication and multimedia
system design. Alta's tools enable system-level design with paths into
both hardware and software. In the path to hardware, HDS (Hardware Design
System) makes it very easy to capture and verify an ASIC block or system
and quickly realize it in FPGAs. This implementation in FPGAs can be used
for rapid prototyping to quickly provide a software integration platform
or it can be used for high volume applications where continued design flexibility
is important. These capabilities are especially useful in many telecommunications
applications, where Alta is the market leader.
The Hardware Design System (HDS) is above traditional HDL-based design
tools. HDS uses parameterized libraries of blocks that enable non-HDL users
to quickly capture and verify an ASIC architecture. Designers can easily
make changes by setting parameters within the design. This flexibility
of parameters enables design re-use. Designs captured in HDS automatically
generate optimized VHDL or Verilog for synthesis and simulation. Many commercial
products have been successfully designed with the Alta tools. These include
cable modems, pagers, cellular and PCS phones, satellite modems, video
encoders, as well as applications in disk drives, medical imaging, and
other signal processing intensive applications
Product Highlights
- Very easy to use
- Super fast simulation
- Large number of parameterized libraries
- Pre-captured communications and multimedia expertise
- Optimized links to synthesis with VHDL and Verilog
- Great signal processing waveform analysis and debugging
Xilinx-Specific Highlights
- HDS generates explicit HDL that can be mapped directly to X-BLOX by
synthesis tools
- HDS parameterized libraries are intuitive to X-BLOX users but are much
more powerful for signal processing applications like communications and
multimedia
Design Flow
Users capture a system level testbench in SPW (Signal
Processing Worksystem) and HDS for communications and video design. The
designer then captures an ASIC architecture design for one or more sub-blocks
in the system design. The ASIC block captured in HDS is verified in a system
level testbench. Once the design performs correctly in the testbench, HDS
automatically generates optimized VHDL or Verilog for synthesis to FPGAs.
After synthesis, the HDL netlist can be re-verified using functional test
vectors captured from the system level testbench.
Product Highlights
- Fast HDL synthesis
- Transparent migration to ASICs
- Powerful waveform language (DWL)
- Automatic schematic generation
- Built-in static timing analyzer
- Powerful waveform viewer
Xilinx-Specific Highlights
- Supports Xilinx XC3000, XC4000, and XC7000 devices
- Design Flow
- EDS supports both schematic entry, EDIF (netlist and schematic) and
industry standard HDL design methodologies.
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