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Xillas
ASTER Ingnierie S.A.
25, rue des Landelles
35510 CESSON-SEVIGNE - FRANCE
Tel: +33-99 53 71 71
Fax: +33-99 51 97 08
XILLAS software automatically converts Xilinx designs into simulation
models for use by LASAR logic simulator.
Product Highlights
- Supports Xilinx XC3000, XC4000, and XC7000 devices
- Generates full LASAR models including min/max propagation delay, timing
constraints, hold, setup, minimum pulse width, and wire loading delay
- Operates on PC, Open VMS VAX, Sun 4-OS and HP-9000 Series 700-HP-UX
Xilinx-Specific Highlights
- Worst-case simulation for PC board functional test program development
and timing certification
- Supports all revision of LCANET format
Design Flow
- XILLAS uses the XNF file and generates a structural description, which
includes functional timings and family characteristics. All timing values
are derived directly from the XNF file and Xilinx Data Sheet.
- LASAR can predict how your Xilinx devices will behave on a PC board
with exceptional accuracy because it provides full dynamic simulation analysis.
- Worst-case or min/max timing
- Proper X handling
- Full signal strength analysis
- Correct bidirectional bus handling
- Board simulation is only as accurate as the models you use
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