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FPGA APS
Auspy Development Inc.
10430 S. DeAnza Blvd., Suite 275
Cupertino, CA 95014 U.S.A.
Tel: 1-408-252-5813/5812
Tel: 1-408-252-5812
Fax: 1-408-252-2582
info@auspy.com
http://www.auspy.com
Auspy is committed to provide solutions for design size over a single
FPGA. APS compliments Xilinx XACTstep software to make multiple-FPGA design
as easy as the single-FPGA one.
Product Highlights
- Partition into minimum number of FPGAs
- Target unlimited number of FPGAs in heterogeneous environment
- ECO capability to minimize changes in inter-FPGA interconnections
- Incremental signal probing
- Handle million-gate + designs
Xilinx-Specific Highlights
- Generating Time Spec. in individual Xilinx chip
- Generating Skew constraint in individual Xilinx chip
- Automatic insertion of GBUF for skew minimization
- Producing script to run Xilinx ppr automatically
- Backannotate ppro result for timing simulation
- Backannotate ppr result for preserving pin locations in ECO
Design Flow
Partition the ASIC/FPGA netlist into the minimum number of target FPGA
netlists ready for the Xilinx ppr.
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