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Timing Designer
Chronology Corporation
8405 165th Avenue N.E.
Redmond, Washington 98052
Tel: 1-206-869-4227
Tel: 1-800-800-6494
Fax: 1-206-869-4229
TimingDesigner is a top-down, timing design tool used to specify, analyze,
and document digital circuit timing. TimingDesigner models complex digital
circuit timing by combining an interactive timing diagram editor with a
dynamically linked timing spreadsheet.
The engineer first creates an ""intelligent"" timing
diagram with the timing diagram editor, which shows the waveforms (sequence
of events), delays (cause and effect relationships), and timing constraints
of a proposed design. The spreadsheet is then used to establish the min./max.
values of each delay and constraint. These values may be complex formulas,
so that path delays, different rise/fall times, loading, temperature, and
other effects can be accurately modeled.
After each modification, TimingDesigner's static timing engine instantly
traces all delay paths specified in the timing diagram, removes common
delays, adjusts for delays which track, selects the critical paths, and
then computes the worst-case timing margins by comparing the total delay
along each critical path to the minimum or maximum allowable value specified
in each constraint. Because design changes are seen instantly, far more
timing alternatives can be evaluated in a short time than with any other
method.
QuickBench is a visual test bench generator which converts intelligent
timing diagrams into self-checking models for use with an HDL simulator.
QuickBench can knock months off an ASIC development schedule by allowing
complex testbenches to be described visually, using timing diagrams.
QuickBench models are used during an HDL simulation to stimulate the
inputs and automatically respond to the resulting outputs, reporting errors
as necessary. This is done by surrounding the design under test with an
""intelligent"" layer of HDL code that models the rest
of the system. QuickBench creates self-checking models that dynamically
respond to the design under test.
Without QuickBench, designers usually develop testbench models manually,
which is very time consuming, or they purchase expensive models from third-party
suppliers. However, since many of the models they need are often not available
for system components, designers are forced to quickly put together a model
manually or find a way to simulate without them. This often results in
an inadequate testbench to ensure accurate simulation.
Using the QuickBench timing diagram editor, users enter a timing diagram
for each type of cycle to be executed. QuickBench automatically translates
these diagrams into VHDL or Verilog models. QuickBench can also access
timing diagrams through Chronology's Synchrony program. Synchrony's Interactive
Databooks consist of interactive timing diagrams for many popular parts
and are fully endorsed by major semiconductor vendors.
Product Highlights
- Interactive Timing Diagram Editor
- Dynamically linked parameter spreadsheet
- Integrated Static Timing Engine
- Hierarchived Library Support
- Complementary to other EDA tools
Xilinx-Specific Highlights
- Supports all Xilinx devices
- Can be used for specification, certification, and documentation
Design Flow
TimingDesigner is used at the beginning of the design process to establish
specifications that can be used in the synthesis and place and route of
Xilinx devices. Results can then be compared to specifications and communicated
to the rest of the design team.
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