LOG/iC

ISDATA
Daimlerstr. 51
D-76185 Karlsruhe Germany
Tel: (49) 721-751087
Fax: (49) 721-752634
isdata@isdata.de
http://www.isdata.de

ISDATA, founded in 1982, is a German company focused on EDA tools for CPLD and FPGA design. ISDATA's special attention lies on the implementation of powerful synthesis algorithms combined with an easy to use tool set.

The LOG/iC2 series is sold worldwide through distribution partners. It is a tool set developed for medium and large CPLD and FPGA applications including timing simulation. It offers various design entries: VHDL, LOG/iC HDL, macrogenerator, vendor macros, 74xx elements.

The hierarchical design style is supported by the graphical hierarchy editor. The stimulus for the simulator may be generated by a test program or, as a unique feature, interactive. For PLD and CPLD synthesis, ISDATA has the proprietary FACT optimizer, known to be the only product term optimizer generating no redundant terms at all. For FPGAs, LOG/iC2 uses technology-oriented optimization algorithms like the functional decomposition for Xilinx LCAs. This means the design is directly mapped to the look up table structure and this leads to less CLBs and faster circuits.

Product Highlights

• Vendor independent design system for PLDs, CPLDs, FPGAs
• Hierarchical design entry
• Various entry methods; VHDL, LOG/IC HDL, macros, library elements
• Generic macro generator for all technologies
• Interactive functional and timings simulation
• Technology oriented optimization

Xilinx-Specific Highlights

• Direct mapping on look-up tables, flip flops, and TBUFs
• Support of X-BLOX, macros and Xilinx primitives
• Automatic use of I/O buffers and I/O flip flops
• Generation of XNF netlist
• Supports XC3000, XC4000, XC5000, XC7000 devices

Design Flow

Typically you do a top-down design starting with the graphical hierarchy editor, which looks similar to a schematic editor. Each symbol can represent one of the following possible entry methods: VHDL, LOG/iC HDL, LOG/iC2 macrogenerator modules, Xilinx macros, X-BLOX, macros, 74xx elements.

You can simulate each module of your design separately or the design as a whole. The stimulus for the simulator may be generated by a test program or interactive. After the technology-oriented optimization (which generates a XNF netlist for the Xilinx devices) and the place and route by the Xilinx tools, a post-layout simulation can be performed.