ASYL+
MINC Incorporated
6755 Earl Drive
Colorado Springs, CO 80918, U.S.A.
Tel: 1-719-590-1155
Fax: 1-719-590-7330
salesinfo@minc.com
http://www.minc.com
France
MINC-IST (subsidiary of MINC)
Europole - 4, place Robert-Schuman - F 38000 Grenoble
GRENOBLE FRANCE 38000
Tel: (33) 76 70 51 00
Fax: (33) 76 84 12 61
info@ist.fr
MINC, together with MINC-IST, provides the broadest programmable logic
synthesis tool. Starting from a large VHDL and Verilog language coverage,
the toolset offers efficient hierarchical architectural synthesis, including
resource optimization (macro inference and folding) and a set of unique
target specific FPGA mapper and CPLD fitters. MINC-IST also provides an
automatic partitioning tool and a highly efficient ASIC synthesis tool,
which are available on workstation and PCs.
ASYL+ uses advanced algorithms to get the best possible performance
and density from your Xilinx devices. With specific mappers for each type
of device, the synthesis power of ASYL+ spans the whole range of Xilinx
devices.
ASYL+ uses proprietary mappers based on innovative synthesis methods
involving binary decision diagram representation for the Xilinx XC3000,
XC4000, and XC5000 families providing true F, H mapped networks for place
and route by Xilinx tools. For the XC7000 families, CPLD methods are used
to optimize the filling of the devices. Both XNF and PLUSASM outputs are
provided. Notice also the powerful finite state machine extraction, especially
adapted to CPLD parts.
ASYL+ offers a level of VHDL and Verilog support as good as any synthesis
tool (even the most expensive) and yet is available at a price which FPGA
users can afford.
To leverage the benefits of a true top-down design, ASYL+ optimizes
the use of Xilinx parameterized generators, thereby creating macroblocks
using the large variety of Xilinx arithmetic basic cells.
Working from a single large netlist or a netlist hierarchy, the MINC-IST
partitioner automatically splits the design across multiple devices in
the Xilinx FPGA families. Mapping directly on the logic blocks of the target
devices, the MINC-IST partitioner both maximizes device filling ratios
and maintains timing control so that critical paths are automatically kept
within package boundaries.
Product Highlights
- User timing-driven synthesis
- Dedicated mappers for all targets
- Broad VHDL and Verilog coverage
- Powerful macro interface
- Hierarchical processing of large design
- Industry standard design languages coupled with architectural synthesis
Xilinx-Specific Highlights
- Dedicated mappers for XC4000/XC5200/XC7000/XC4000E
- Timing constraints driven synthesis
- Inference of X-BLOX
- Broad VHDL and Verilog support
- Hierarchical design processing
Design Flow
ASYL+ offers both VHDL and Verilog, with a very broad set of constructs
for describing even the most complicated logic in a compact fashion. Dedicated
macrogenerators makes designing with arithmetic modules, counters, and
shifters a breeze, and provides an advantage in performance and compactness
of the design. Vendor macros, such as ACTGEN and X-BLOX, are inferred from
the design description and implemented to improve performance. State machines
found in the VHDL description are extracted with state assignment encoding
either automatically selected for the most compactness or selected by the
user. Common logic is recognized and can be shared to match the performance
requirements of the circuit instead of being built several times, thus
saving silicon area.
MINC-IST has developed specific algorithms to squeeze the last ounce
of performance from programmable logic devices, as well as specific optimization/mappers
specifically designed for each device architecture to provide the best
results. Many optimizers use several algorithms which are run, and the
results then compared with the best chosen for the job. Binary Decision
Diagrams (BDD's), Lexicographical, and Boolean Matching are a few of the
techniques that are used in the specific mappers, in addition to complex
logic collapsing. Optimization is constraint driven and completely controlled
by the user.
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