Silos III
Simucad, Inc.
32970 Alvarado-Niles Road
Union City, CA 94587 U.S.A.
Tel: 1-510-487-9700
Fax: 1-510-487-9721
silos@simucad.com
http://www.simucad.com
The SILOS III Simulation Environment is the latest advancement in Verilog
HDL-based digital simulation technology. SILOS III is the only HDL simulator
offering interactive logic and fault simulation at all levels of abstraction.
Verilog HDL is fully supported at the behavioral, gate, and switch levels.
There is even support for the new analog behavioral modeling extensions.
SILOS III delivers the performance of a compiled technology simulator while
retaining the debugging attributes of a high speed interpreted simulator.
SILOS III's performance, even on a PC, will rival the competition's
workstation-based simulators, thus providing a significant price-to-performance
advantage for your hardware and software investment. Whether your design
environment is PC or UNIX workstation, SILOS III's superior performance,
memory utilization, and outstanding capabilities can address all of your
logic and fault simulation requirements.
Product Highlights
- An open architecture allows SILOS III to interface with other software
tools
- A help system provides on-line assistance at any point in the simulation
process
- An extensive array of primitive logic elements and complex gate models
are provided
- SILOS III is available for Windows, WinNT and UNIX computers
- Supports multiple design input formats, including combined logic schematics,
Boolean equations, and state machine descriptions
Xilinx-Specific Highlights
- Supports Xilinx XC3000 and XC4000 device families
- Supports post-layout timing analysis
- Input automatically generated from Xilinx XNF files
- Simulates logic complexities up to 16,000 gates
- Operates on personal computers running Windows or Windows NT
Design Flow
After design entry, simulation may be used to functionally verify logic.
This saves design time because logic errors can be detected and corrected
prior to final placement and routing. After a circuit has been placed,
routed, and fully debugged using in-circuit emulation, worst-case timing
may be verified. This enables the user to select the correct FPGA speed
grade for a particular application.
Simulation netlist inputs for FPGA designs are automatically created
by the XNF2SILO utility. The network includes logic and routing-delay parameters,
and set-up and hold times based upon the selected speed grade operating
under worst-case conditions. Simulation stimuli are created with a set
of clock statements or with an input pattern for either pad inputs or internal
nodes. Simulation results are available in tabular, plotted and graphical
formats. This flexibility makes the ""logic debug""
easy for both the circuit function and timing.
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