Vanguard

(Worldwide, except Japan)
Sophia Systems and Technology
711-B Charcot Ave
San Jose, CA 95131 U.S.A
Tel: 1-408-943-9300
Fax: 1-408-943-9303

Sophia Systems and Technology supplies a powerful, easy-to-use tool that translates a Vanguard schematic design into a Xilinx Netlist File (XNF). Any XNF component, pin, or signal parameter can be expressed as a property in the Vanguard Schematic.

A library of over 700 Xilinx soft macros with corresponding schematic components is included. Xilinx CLB and IOB blocks may be configured directly from the schematic through the CLB, IOB, and MAP symbols. Vanguard schematics are created using the Vanguard Design Environment. This environment includes a powerful, function-rich, design entry tool that runs on the PC and workstations. In addition to Xilinx FPGA development, the Vanguard Development Environment supports PLD, custom ASIC, and PCB design.

Product Highlights

• Full support for Xilinx XC3000, XC3100, and XC4000 devices
• Powerful, configurable design entry system
• Runs on PCs, and Sun and VAX workstations
• Tutorial and demonstration files included with the translation tool

Xilinx-Specific Highlights

• Provides open, powerful, flexible design environment for Xilinx devices
• Outputs XNF netlist
• Allows use of MAP-THEN-MERGE methodology

Design Flow

1. Your FPGA design is input as a schematic using Vanguard schematic capture tools and Vanguard supplied Xilinx-specific component libraries.
2. The Vanguard-to-Xilinx interface (TOXNF) translates the schematic design into the Xilinx netlist file.
3. XNF files are manually merged into the XC3000 designs and automatically merged in XC4000 designs. Place and route programs and design post processing tools are part of the XACTstep development system.