WaveFormer Pro  

WaveFormer Pro by SynaptiCAD is an EDA tool for digital designers. WaveFormer Pro can be used for: timing analysis, stimulus generation, Boolean simulation, waveform viewing, and timing diagram documentation. 

WaveFormer Pro is a synergistic combination of 3 tools in one: a timing diagram editor, an interactive HDL simulator, and a stimulus generator. With WaveFormer Pro you begin your design cycle by constructing timing diagrams that define your system requirements using the timing diagram editing and Boolean simulation features. The Logic Wizard allows you to rapidly design digital circuits without having to create schematic or HDL models to verify basic functionality. The timing diagram editing features calculate critical timing paths and automatically assure that timing requirements are met. If you then simulate your design, you can use the stimulus generator features to export your waveforms to drive the Xilinx Foundation Kit simulator, or your favorite gate-level or HDL simulator for a final check on system. Finally, when it comes time to document your system, your work is already half done since you can create professional quality documentation for your design from the timing diagrams you created at the beginning of your design process (they're also great for impressive design reviews). 

Product Highlights 

• Interactive HDL Simulator
• Timing Diagram Editor
• VHDL, Verilog & SPICE Stimulus Generator

Xilinx-Specific Highlights

• Support for all Xilinx devices
• Export stimulus to Xilinx Foundation Kit simulator
• Circuit verification and documentation

The timing diagram editor features allows users to interactively perform timing analysis on their waveforms and document timing relationships using delays, setups, holds, samples, and textual information.  The Boolean equation generator lets the user quickly model complex combinatorial logic complete with propagation and interconnect delays and see the effect on overall system timing.  The HDL-based interactive simulator support registered PLD-type equations, direct simulation of Verilog equations, and iterative signal calculation that automatically updates when input signals change.  The digital stimulus generator enables users to import, export, and translate digital waveform stimulus to drive simulators and test equipment (supports VHDL/Verilog/SPICE and many gate level simulators).  These functions combine to form a powerful new way to design and document digital systems. 
 

TestBencher Pro 

TestBencher Pro generates reactive, self-testing VHDL and Verilog test benches that greatly reduce design cycle time. 

 TestBencher Pro generates reactive Verilog and VHDL bus-functional models and test benches directly from timing diagrams, significantly reducing the time needed to verify your designs. The generated code is small, similar to manually coded test benches, so it is easy to understand and integrate with existing code. TestBencher Pro can detect glitches, invalid logic levels, and violations of setup and hold times in simulation output. It also supports looping and conditional stimulus vector generation. 
 TestBencher Pro is particularly useful for generating test benches that simulate the interaction of processors and other complex VLSI ICs with an outside system designed by the user. Full HDL models are often not available for these complex parts, but timing diagrams that describe their bus protocols (e.g. read, write, DMA, interrupt cycles) are generally available. Users can enter these timing diagrams graphically into TestBencher Pro and then control the sequencing of these cycles to the system being simulated. The timing diagrams can include setup and hold time requirements that must be met by the system in order to properly communicate with the processor. At simulation time, appropriate warning messages will be generated if these requirements are violated. 

Product Highlights 

• Generates customizable, reactive test benches in VHDL & Verilog
• Generates Bus Functional Models for VHDL & Verilog
• Interactive HDL Simulator
• Timing Diagram Editor
• VHDL, Verilog & SPICE Stimulus Generator

Xilinx-Specific Highlights

• Support for all Xilinx devices
• Export stimulus to Xilinx Foundation Kit simulator
• Circuit verification and documentation
• Reactive self-testing test benches

With TestBencher Pro, users generate a series of timing diagrams that represent reusable timing transactions (e.g. read cycle, write cycle, interrupt cycle) using a built-in timing diagram editor. In the timing diagram users specify both input and expected output waveforms. Graphically specified parameters called samples are placed on the expected output signals. These samples generate the HDL code which verifies that user-defined conditions are met during simulation. Samples can detect simulation problems such as glitches, bad logic levels, and violations of setup and hold times. Users can select what action to take when a sample condition is not met during simulation. Possible actions include: applying a different set of test vectors (from a different timing diagram), outputting a warning to a log file, generating a break to a debugger, aborting the simulation, or a user-defined action.