VBAK

Topdown Design Solutions, Inc.
71 Spit Brook Road, Suite 301
Nashua, NH 03060 U.S.A.
Tel: 1-603-888-8811
Fax: 1-603-888-7694
sales@topdown.com
http://www.topdown.com

Topdown's VBAK family puts the advantages of VHDL-based design within reach of every Xilinx designer. With VBAK/VITAL's VHDL generator and validated XNF primitives library, you can enjoy accurate post-layout timing simulation with the high-powered affordable Model Technology V-System simulator. With VBAK/SST's high-level VHDL generator, you get the speed benefits of RTL based simulation with V-System or VHDL simulators, and you can use popular FPGA synthesis tools to easily retarget XNF designs within or across Xilinx families. Available for both UNIX and Windows, VBAK is the simple cost-effective solution for Xilinx VHDL design.

Product Highlights

• Enables HDL-based design by generating VHDL from any XNF file
• VBAK/VITAL produces gate-level VHDL for post-layout simulation
• VBAK/VITAL supports MTI V-SYSTEM simulator for UNIX and Windows
• VBAK/SST creates an RTL VHDL model for simulation and synthesis
• VBAK/SST supports all 1076-standard VHDL simulation and synthesis tools

Xilinx-Specific Highlights

• Supports XC3000, XC4000, XC4000E, and XC5000 families
• VBAK/VITAL back-annotates post-layout timing from XACT
• VBAK/VITAL offers VITAL level 1 VHDL simulation with XACT
• VBAK/SST enables VHDL synthesis for easy retargeting among Xilinx families

Design Flow

Use VBAK/VITAL for highly accurate gate-level VHDL timing simulation from any post-layout or post-synthesis SNF files, regardless of the original source of your design. Use VBAK/SST to enable quick functional VHDL simulation at any phase of the design process, including the rapid verification of your FPGA within its target system. Also use VBAK/SST to enhance existing, possibly, undocumented FPGA designs by translating XNF to high-level VHDL for easy editing, simulation and synthesis. Even use it to retarget multiple FPGAs to a larger single design or to switch among FPGA families for an optional implementation.