Boundary Scan/JTAG: Glossary
1149.1
- IEEE standard describing the Test Access Port and Boundary Scan Architecture.
ATE
- Automatic Test Equipment.
Boundary Register
- The Boundary Scan Data Register that has a Boundary Scan cell adjacent to each input and output pin of the IC.
Boundary Scan
- Boundary Scan is the informal name for the IEEE Standard 1149.1.
BSCAN
- A Xilinx library symbol that must be instantiated in the schematic or the HDL design targetting a XC4K/XC5K device, if Boundary Scan is desired to be used after Configuration.
BSDL
- The Boundary Scan Description Language that describes the features of the device under test.
BYPASS
- A mandatory 1149.1 instruction that effectively disconnects the internal logic of the IC from the system.
Bypass Register
- The Boundary Scan Data Register that is used by the BYPASS instruction.
Configuration
- The process of programming an FPGA. Configuration occurs during power up and can
optionally occur if a reprogram has been initiated.
Data Protect
- A bit in the XC9500 device, when set, renders the CPLD unreadble, thereby protecting the programmed information in the part.
Data Register
- A Boundary Scan Register that is selcted by a TAP Instruction.
EPIC
- A Chip Viewer for the FPGAs supplied with the Xilinx M1.x software.
ERASE
- A XC9500 Boundary Scan instruction that clears the device programming information.
EXTEST
- A mandatory 1149.1 instruction that is used to capture data at the inputs and outputs of the IC.
EZTAG
- Xilinx XACT 6.x version software used for Boundary Scan operation of the XC9500 devices.
FSM
- Finite State Machine.
Functional Simulation
- Simulation of a logical netlist using unit delays.
HDL
- Hardware Description Language. A language which describes circuits
in textual code. The two most widely accepted HDLs are VHDL
and Verilog.
IC
- An acronym for Integrated Circuit.
IEEE (pronounced "I
triple-E")
- Institute of Electrical and Electronics Engineers.
Instruction Register
- A Shift Register used for shifting and storing the TAP instructions.
ISP
- An acronym for In-System Programming. Describes the process of programming a device while it is still in the circuit.
JTAG (pronounced "J-tag")
- The Joint Test Action Group. This group created the foundation for the IEEE work.
JTAG Cable
- Xilinx Parallel Cable III, Model DLC5 is also known as the JTAG cable.
JTAG Programmer
- Xilinx M1.x version software used for Boundary Scan operation of the XC9500 devices.
PROGRAM
- A XC9500 Boundary Scan instruction that configures the device.
READBACK
- A XC4K/XC5K Boundary Scan instruction that allows the user to read back the data and the states of internal registers from a configured device.
Scan Educator
- A DOS based Boundary Scan educational software written by
SAMPLE/PRELOAD
- A mandatory 1149.1 instruction that allows the user to sample the data at the IC's inputs as well as preload the inputs with known data.
TAP
- The Boundary Scan Test Access Port. It is formed by the TDI, TDO, TCK, TMS and the optional TRST pin.
TAP Controller
- A sixteen state FSM that controls the Boundary Scan logic on the IC.
TCK
- Test Clock, a TAP pin used to supply clocks to the TAP Controller.
TDI
- Test Data In, a TAP pin used to shift the test data in to the TAP Controller.
TDO
- Test Data Out, a TAP pin used to shift the test data out from the TAP Controller.
Test-Logic-Reset
- The state of the TAP Controller on power up. All Boundary Scan logic is disabled in this state.
TMS
- Test Mode Select, a TAP pin that provides the stimulus to change the state of the TAP Controller.
TRST
- Test Reset, an optional TAP pin used to drive the the TAP Controller to the Test-Logic-Reset state on assertion.
Verilog
- An industry-standard HDL developed by Cadence
Design Systems. Recognizable as a file with a .v extension.
VHDL
- VHSIC Hardware Description Language. An industry-standard
(IEEE 1076.1) HDL. Recognizable
as a file with a .vhd or .vhdl extension.
VHSIC
- Very High Speed Integrated Circuit.
XCHECKER Cable
- Xilinx Serial cable, model DLC4 is also known as the Xchecker cable.
XDE
- Xilinx Design Editor, a chip viewer for the FPGAs available with the XACT 5.x, 6.x versions of software.
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