FPGA Advisor

Mentor Graphics
8005 S.W. Boeckman Road
Wilsonville, OR 97070-7777 U.S.A.
Tel: 1-800-547-3000
Fax: 1-503-685-8001
http://www.mentorg.com

The Mentor Graphics environment supports a variety of paths to Xilinx XACTstep software, as well as return paths from XACTstep. Designers of Xilinx devices can use XACTstep primitives to build a schematic, use VHDL to specify RTL that is then synthesized and optimized for the target device family, use graphical state machine and data path specifications that automatically create the synthesizable VHDL, or any mixture. For post-layout timing verification, back annotation paths to simulation are supported. These capabilities are all encompassed in the Top-down Design Solver suite of tools, and in the Top-down FPGA Station family of tools.

Product Highlights

• Support for all device families with Design Architect and QuickSim II
• Support for XC3000, XC4000, XC4000E, XC5200, and XC7000 device families with Autologic II
• Full compatibility with ASIC and board design environments
• High-performance and capacity for maximum designer productivity
• Available on Sun SPARC and HP 700 platforms

Xilinx-Specific Highlights

• Proven design flow used by thousands of designers
• Architecture-specific logic optimization in AutoLogic
• Full back-annotation path to QuickSim II
• Full design kit encapsulation in Falcon framework

Design Flow

Starting from any blend of schematics, RTL descriptions, state machines, boolean equations or parameterized data path elements, the design is synthesized, optimized, simulated and merged (as appropriate) in the Mentor Graphics environment. The design is passed to and from the XACTstep tools using netlisters provided in the Xilinx Design Kit. After the place and route is performed, the layout delays are back-annotated into QuickSim II for verification of actual timing of the target device. Extensive debugging aids are provided at each step in the flow, with on-line help and documentation available. The result: fast time-to-market.