 Synplify
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Synplicity is the leader in high quality FPGA/CPLD synthesis tools. Synplify
is an FPGA/CPLD Synthesis tool that synthesizes Verilog and VHDL designs
into small, high performance XNF netlists for Xilinx devices using proprietary
custom algorithms that map directly to the Xilinx architectures. Synplify
runs up to 100 times faster than other synthesis tools while delivering
the highest quality of results through special optimization, mapping, and
module generation techniques. Synplify also includes a language sensitive
editor with syntax and synthesis checker to highlight problems and quickly
resolve them for maximum productivity.
Synplify runs on Sun and HP workstations, and PCs using the Windows
95 or Windows NT operating system.
Synplify Product Highlights
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Symbolic
FSM Compiler which automatically identifies, extracts and re-encodes
state machines
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Extremely Fast Runtime (100k gates in 10 minutes)
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Comes with the Synplify Editor, an integrated language-sensitive
editor with syntax and synthesis checking
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Supports synthesizable IEEE 1076-1993 and 1164 VHDL, and IEEE 1364 Verilog
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Supports the major Xilinx device families, including the new EX series
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Runs on Suns and HPs and PCs
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Extremely Easy to Use and Intuitive
INTRODUCING--Synplify
3.0 & HDL Analyst-Available July 1, 1997
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HDL Analyst-New option that automatically
generates RTL and Gate-level schematics from the Verilog or VHDL source
code allowing the designer to easily view HDL source, RTL schematics (block
diagram) and the Gate-level schematic at the same time while performing
bidirectional crossprobing between each of the Views.
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TCL Scripting capability for setting timing
constraints, invoking other tools, and performing multiple synthesis runs
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Resource Sharing allowing Synplify to share
logic resources and yielding improved area results
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Option to output Verilog and/or VHDL netlist
Xilinx-Specific Highlights
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Maps directly to Xilinx's FMAPs, HMAPs, and XBLOX.
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Maps directly to Xilinx's Relatively Placed Macros (RPMs) for Xilinx XC4000,
bypassing XBLOX completely.
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Infers counters, adders, subtractors, etc., and performs module generation.
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Automatically uses the flip-flop load enable, GSR, and clock buffer resources.
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Automatically inserts I/O's and uses the flip-flops in I/Os as appropriate.
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Supports passing input setup and output transition time preferences to
Xilinx.
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Cleanly supports instantiating library primitives and black boxes.
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The Synplify timing report takes routing effects into account.
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M1 Flow-generates RPMs differently for the M1 release
to allow M1 to specify the direction (up or down) of the carry chain, improving
routability.
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Synplify Xilinx only version available through Insight
Electronics.
Design Flow
Create your VHDL or Verilog Design. You can use one of many examples provided
as basis for your design. Don't forget to perform a syntax and synthesis
check in the Synplify Editor. Synplify will highlight any errors in your
code so you can get the bugs out quickly. After you correct any problems,
check the logical correctness of your design with a logic simulator. In
Synplify, give your source file name, your target device, and click the
RUN button to synthesize your design. Synplify will generate an XNF file
that contains your optimized design netlist for Xilinx. Run Xilinx XACT
to place and route, and program your part. XACT will generate a timing-annotated
XNF netlist to read into your logic simulator so that you can perform a
final functional simulation after place and route.
For a presentation and demonstration of the Synplify software, as well
as the opportunity to load the Synplify software, click Demonstration.
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