-- @(#)vlbcomp.vhd 1.2 9/17/97 ---------------------------------------------------------------- -- -- Created by Gooby -- FILENAME : vlbcomp.vhd -- FILE CONTENTS: component and entity lib for xc6000 primitives -- DATE CREATED : Tue Oct 29 1996 -- -- LIBRARY : xc6000 -- TECHNOLOGY : cmos -- TIME SCALE : 1 ns -- LOGIC SYSTEM : IEEE-1164 -- NOTES : -- HISTORY : 25 June 1997 - Big update to include description of prims -- : 17 Sept 1997 - Release for web site. -- ---------------------------------------------------------------- package xc6000_components is ----- Component AND2 ----- -- Behavior: O <= I0 AND I1 component AND2 port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end component; ----- Component AND2B1 ----- -- Behavior: O <= !I0 AND I1 component AND2B1 port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end component; ----- Component AND2B2 ----- -- Behavior: O <= !I0 AND !I1 component AND2B2 port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end component; ----- Component BUF ----- -- Behavior: O <= I component BUF port( O : out STD_LOGIC; I : in STD_LOGIC); end component; ----- Component BUFGP ----- -- Behavior: O <= I (Decorate with GLOBAL attribute to use as clock buffer) component BUFGP port( O : out STD_LOGIC; I : in STD_LOGIC); end component; ----- Component CBUF_IN ----- -- Behavior: Underlying control wire <= I (R/CSIGNAL attributes apply) component CBUF_IN port( I : in STD_LOGIC); end component; ----- Component CBUF_INSIM ----- -- Behavior: CSIG <= I (For simulation) component CBUF_INSIM port( I : in STD_LOGIC; CSIG : out STD_LOGIC); end component; ----- Component CBUF_OUT ----- -- Behavior: O <= Underlying control wire (RSIGNAL attribute apply) component CBUF_OUT port( O : out STD_LOGIC); end component; ----- Component CBUF_OUTSIM ----- -- Behavior: O <= CSIG (For simulation) component CBUF_OUTSIM port( CSIG : in STD_LOGIC; O : out STD_LOGIC); end component; ----- Component FDC ----- -- Behavior: Q <= D on ^C, or <= '0' on ^CLR (^ = rising edge) component FDC port( Q : out STD_LOGIC; D : in STD_LOGIC; C : in STD_LOGIC; CLR : in STD_LOGIC); end component; ----- Component FDP ----- -- Behavior: Q <= D on ^C, or <= '1' on ^CLR (^ = rising edge) component FDP port( Q : out STD_LOGIC; D : in STD_LOGIC; C : in STD_LOGIC; PRE : in STD_LOGIC); end component; ----- Component GND ----- -- Behavior: GROUND => '0' component GND port( GROUND : out STD_LOGIC); end component; ----- Component IBUF ----- -- Behavior: O <= I (Used with IPAD) component IBUF port( O : out STD_LOGIC; I : in STD_LOGIC); end component; ----- Component INV ----- -- Behavior: O <= !I component INV port( O : out STD_LOGIC; I : in STD_LOGIC); end component; ----- Component IOPAD ----- -- Behavior: IOPAD <=> Outside world component IOPAD port( IOPAD : inout STD_LOGIC); end component; ----- Component IOPADSIM ----- -- Behavior: IOPAD <= (FromOBUF AND Control), or => (ToIBUF AND !Control) -- (For simulation) component IOPADSIM port( IOPAD : inout STD_LOGIC; FromOBUF : in STD_LOGIC; ToIBUF : out STD_LOGIC; Control : in STD_LOGIC); end component; ----- Component IPAD ----- -- Behavior: IPAD <= from outside world component IPAD port( IPAD : out STD_LOGIC); end component; ----- Component IPADSIM ----- -- Behavior: IPAD <= I (For simulation) component IPADSIM port( I : in STD_LOGIC; IPAD : out STD_LOGIC); end component; ----- Component LDSIM ----- -- Behavior: Q <= D while G is high (For simulation) component LDSIM port( Q : out STD_LOGIC; D : in STD_LOGIC; G : in STD_LOGIC); end component; ----- Component M2_1 ----- -- Behavior: O <= (D0 AND !S0) OR (D1 AND S0) component M2_1 port( O : out STD_LOGIC; D1 : in STD_LOGIC; D0 : in STD_LOGIC; S0 : in STD_LOGIC); end component; ----- Component M2_1B1A ----- -- Behavior: O <= (!D0 AND !S0) OR (D1 AND S0) component M2_1B1A port( O : out STD_LOGIC; D1 : in STD_LOGIC; D0 : in STD_LOGIC; S0 : in STD_LOGIC); end component; ----- Component M2_1B1B ----- -- Behavior: O <= (D0 AND !S0) OR (!D1 AND S0) component M2_1B1B port( O : out STD_LOGIC; D1 : in STD_LOGIC; D0 : in STD_LOGIC; S0 : in STD_LOGIC); end component; ----- Component M2_1B2 ----- -- Behavior: O <= (!D0 AND !S0) OR (!D1 AND S0) component M2_1B2 port( O : out STD_LOGIC; D1 : in STD_LOGIC; D0 : in STD_LOGIC; S0 : in STD_LOGIC); end component; ----- Component NAND2 ----- -- Behavior: O <= I0 NAND I1 component NAND2 port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end component; ----- Component NAND2B1 ----- -- Behavior: O <= !I0 NAND I1 component NAND2B1 port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end component; ----- Component NAND2B2 ----- -- Behavior: O <= !I0 NAND !I1 component NAND2B2 port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end component; ----- Component NOR2 ----- -- Behavior: O <= I0 NOR I1 component NOR2 port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end component; ----- Component NOR2B1 ----- -- Behavior: O <= !I0 NOR I1 component NOR2B1 port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end component; ----- Component NOR2B2 ----- -- Behavior: O <= !I0 NOR !I1 component NOR2B2 port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end component; ----- Component OBUF ----- -- Behavior: O <= I (Used with OPAD) component OBUF port( O : out STD_LOGIC; I : in STD_LOGIC); end component; ----- Component OBUFE ----- -- Behavior: O <= I AND E (Used with OPAD) component OBUFE port( O : out STD_LOGIC; I : in STD_LOGIC; E : in STD_LOGIC); end component; ----- Component OBUFT ----- -- Behavior: O <= I AND !T component OBUFT port( O : out STD_LOGIC; I : in STD_LOGIC; T : in STD_LOGIC); end component; ----- Component OPAD ----- -- Behavior: Outside world <= OPAD component OPAD port( OPAD : in STD_LOGIC); end component; ----- Component OPADSIM ----- -- Behavior: O <= OPAD (For simulation) component OPADSIM port( O : out STD_LOGIC; OPAD : in STD_LOGIC); end component; ----- Component OR2 ----- -- Behavior: O <= I0 OR I1 component OR2 port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end component; ----- Component OR2B1 ----- -- Behavior: O <= !I0 OR I1 component OR2B1 port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end component; ----- Component OR2B2 ----- -- Behavior: O <= !I0 OR !I1 component OR2B2 port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end component; ----- Component PULLDOWN ----- -- Behavior: O => 'L' component PULLDOWN port( O : out STD_LOGIC); end component; ----- Component PULLUP ----- -- Behavior: O => 'H' component PULLUP port( O : out STD_LOGIC); end component; ----- Component RPFD ----- -- Behavior: Q <= (Q on ^C), or (PC Write on ^C) component RPFD port( Q : out STD_LOGIC; C : in STD_LOGIC); end component; ----- Component RPFDC ----- -- Behavior: Q <= ('0' on ^CLR), or (PC Write on ^C) component RPFDC port( Q : out STD_LOGIC; C : in STD_LOGIC; CLR : in STD_LOGIC); end component; ----- Component VCC ----- -- Behavior: VCC => '1' component VCC port( VCC : out STD_LOGIC); end component; ----- Component XNOR2 ----- -- Behavior: O <= I0 XNOR I1 component XNOR2 port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end component; ----- Component XOR2 ----- -- Behavior: O <= I0 XOR I1 component XOR2 port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end component; end xc6000_components; ---- end of components library ---- library prims; use prims.xc6000_components.all; ----- entity AND2 ----- entity AND2 is port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of and2 is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity AND2B1 ----- entity AND2B1 is port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of and2b1 is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity AND2B2 ----- entity AND2B2 is port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of and2b2 is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity BUF ----- entity BUF is port( O : out STD_LOGIC; I : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of buf is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity BUFGP ----- entity BUFGP is port( O : out STD_LOGIC; I : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of bufgp is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity CBUF_IN ----- entity CBUF_IN is port( I : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of cbuf_in is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity CBUF_INSIM ----- entity CBUF_INSIM is port( I : in STD_LOGIC; CSIG : out STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of cbuf_insim is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity CBUF_OUT ----- entity CBUF_OUT is port( O : out STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of cbuf_out is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity CBUF_OUTSIM ----- entity CBUF_OUTSIM is port( CSIG : in STD_LOGIC; O : out STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of cbuf_outsim is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity FDC ----- entity FDC is port( Q : out STD_LOGIC; D : in STD_LOGIC; C : in STD_LOGIC; CLR : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of fdc is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity FDP ----- entity FDP is port( Q : out STD_LOGIC; D : in STD_LOGIC; C : in STD_LOGIC; PRE : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of fdp is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity GND ----- entity GND is port( GROUND : out STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of gnd is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity IBUF ----- entity IBUF is port( O : out STD_LOGIC; I : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of ibuf is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity INV ----- entity INV is port( O : out STD_LOGIC; I : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of inv is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity IOPAD ----- entity IOPAD is port( IOPAD : inout STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of iopad is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity IOPADSIM ----- entity IOPADSIM is port( IOPAD : inout STD_LOGIC; FromOBUF : in STD_LOGIC; ToIBUF : out STD_LOGIC; Control : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of iopadsim is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity IPAD ----- entity IPAD is port( IPAD : out STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of ipad is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity IPADSIM ----- entity IPADSIM is port( I : in STD_LOGIC; IPAD : out STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of ipadsim is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity SNH ----- entity SNH is port( Q : out STD_LOGIC; D : in STD_LOGIC; G : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of snh is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity M2_1 ----- entity M2_1 is port( O : out STD_LOGIC; D1 : in STD_LOGIC; D0 : in STD_LOGIC; S0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of m2_1 is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity M2_1B1A ----- entity M2_1B1A is port( O : out STD_LOGIC; D1 : in STD_LOGIC; D0 : in STD_LOGIC; S0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of m2_1b1a is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity M2_1B1B ----- entity M2_1B1B is port( O : out STD_LOGIC; D1 : in STD_LOGIC; D0 : in STD_LOGIC; S0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of m2_1b1b is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity M2_1B2 ----- entity M2_1B2 is port( O : out STD_LOGIC; D1 : in STD_LOGIC; D0 : in STD_LOGIC; S0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of m2_1b2 is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity NAND2 ----- entity NAND2 is port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of nand2 is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity NAND2B1 ----- entity NAND2B1 is port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of nand2b1 is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity NAND2B2 ----- entity NAND2B2 is port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of nand2b2 is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity NOR2 ----- entity NOR2 is port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of nor2 is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity NOR2B1 ----- entity NOR2B1 is port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of nor2b1 is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity NOR2B2 ----- entity NOR2B2 is port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of nor2b2 is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity OBUF ----- entity OBUF is port( O : out STD_LOGIC; I : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of obuf is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity OBUFE ----- entity OBUFE is port( O : out STD_LOGIC; I : in STD_LOGIC; E : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of obufe is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity OBUFT ----- entity OBUFT is port( O : out STD_LOGIC; I : in STD_LOGIC; T : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of obuft is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity OPAD ----- entity OPAD is port( OPAD : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of opad is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity OPADSIM ----- entity OPADSIM is port( O : out STD_LOGIC; OPAD : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of opadsim is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity OR2 ----- entity OR2 is port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of or2 is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity OR2B1 ----- entity OR2B1 is port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of or2b1 is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity OR2B2 ----- entity OR2B2 is port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of or2b2 is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity PULLDOWN ----- entity PULLDOWN is port( O : out STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of pulldown is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity PULLUP ----- entity PULLUP is port( O : out STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of pullup is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity RPFD ----- entity RPFD is port( Q : out STD_LOGIC; C : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of rpfd is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity RPFDC ----- entity RPFDC is port( Q : out STD_LOGIC; C : in STD_LOGIC; CLR : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of rpfdc is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity VCC ----- entity VCC is port( VCC : out STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of vcc is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity XNOR2 ----- entity XNOR2 is port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of xnor2 is begin end dummy; library prims; use prims.xc6000_components.all; ----- entity XOR2 ----- entity XOR2 is port( O : out STD_LOGIC; I1 : in STD_LOGIC; I0 : in STD_LOGIC); end entity; library prims; use prims.xc6000_components.all; architecture dummy of xor2 is begin end dummy; ---- end of entitys library ----