Device Replacement Guide -
XC4000H Family

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Purpose

This Device Replacement Guide is designed to help customers who are in production with a Xilinx FPGA that is planned to be made obsolete. General guidelines are given for how to convert an existing XC4000H design to an alternative Xilinx FPGA device. This guide details devices that are pinout compatible with the XC4000H device and outlines the main differences that must be considered when converting a design.

Reason for Discontinuance

The XC4000H devices were introduced to offer customers a higher I/O-to-gate ratio than was available with our previous FPGA families. The XC4000H provided a more competitively priced solution for applications with a large I/O requirement but a density requirement of less than 5,000 gates. With the dramatically lower device costs of the XC4000E and XC5200 familes, and the trend towards higher density customer designs, these newer familes now offer a better balance between I/O count, density and cost.

Timeline

Conversion Guidelines and Considerations

The devices listed in Table 1 are pin-for-pin replacements for designated XC4000H devices. They are not however, bitstream compatible. Designs must therefore be recompiled through the XACT^R tools.

Replacement Devices will be equivalent or lower priced than current devices in all cases.

The existing design was probably implemented in the XC4000H device because of the I/O capabilities, especially the large number of I/O. Therefore, a larger XC4000E or XC5200 device must be used for the replacement design. For example, if all 160 I/O in an XC4003H are used, an XC4010E or XC5210 is required to provide the same number of I/O.

If converting to an XC4000E device, schematic changes may not be necessary. Except for the I/O capabilities, XC4000E devices have all of the same features as XC4000H devices (see Table 2). One I/O feature not included in the XC4000E is the 24 mA drive capability of the XC4000H (in resistive mode). In switching to the XC4000E, output pins may need to be paired in order to sink the required output current. This will affect the board design. Another exception is the more flexible output slew rate in the XC4000H, which offers Resistive Load and SoftEdge^TM (default) options not available in the XC4000E. If large numbers of I/O switch simultaneously in the design, change "RES" and "CAP" parameters on I/O to "FAST" only where needed. Also, the XC4000H has the capability of assigning TTL or CMOS I/O levels on a per-pin basis, while the XC4000E has only global assignment capability. All inputs have the same threshold, and all outputs drive the same level, although input thresholds and output levels can be independently assigned. TTL inputs can of course interpret both CMOS and TTL levels, so this limitation is not really an issue. If re-translating the schematics, remove "TTL" or "CMOS" parameters, and include CMOS selection in XMake/Flow Engine if desired.

When moving from an XC4000H to an XC4000E, use a speed grade two levels faster than the original speed grade (i.e., move an XC4000H-5 to an XC4000E-3, and an XC4000H-6 to an XC4000E-4). Although the majority of specifications are faster in the XC4000E than in the XC4000H, a few parameters are slower, so this conservative approach is recommended for a first pass. Use XDelay and simulation to verify performance prior to production.

If converting to an XC5200-family device, a larger number of changes may be required, as the architecture of the internal CLB array is significantly different. The most significant difference between the XC5200 and the XC4000H is that the XC5200 does not include RAM (see Table 2). For designs without RAM, the XC5200 is probably the most economical choice. Wide edge decoders are also not provided. Instead, the XC5200 includes general-purpose cascade circuits that can be used to implement decoder logic. Schematic alterations are required. There are other differences between the families, as well. These are described in detail in the Xilinx Application Note, "Design Migration From XC4000 to XC5200," available on the Xilinx WebLINX at http://www.xilinx.com. This application note also includes details of the software steps used in the conversion process that may also be useful when converting to the XC4000E.

When moving from an XC4000H to an XC5200, use a speed grade one level faster than the original speed grade for the first pass (i.e., move an XC4000H-5 to an XC5200-4, and an XC4000H-6 to an XC5200-5). Use XDelay and simulation to verify performance prior to production.

Fortunately, with the Xilinx Unified Libraries, most components in a schematic apply equally well to all Xilinx families. However, components using the features discussed above will need to be replaced.

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