CoreEl MicroSystems, Inc.now offers five cores targeted at networking and Asynchronous Transfer Mode (ATM) applications. These have been specifically optimized for Xilinx XC4000 FPGAs, and some also support the new Spartan series devices. All are available directly from CoreEl Microsystems.

Cores Available Now:

50 MHz UTOPIA Slave Transmitter and Receiver Cores Cell Delineation Block Cell Assembler Block CRC10 Generator and Verifier Blocks CRC32 Generator and Verifier Blocks

Target Applications for new Cores
The AllianceCORE products from CoreEl are targetted at developers of ATM communication systems, including network interface controllers (NICs), switches, traffic shapers and traffic rate controllers. They provide the fundamental ATM building blocks for developing flexible NIC, segmentation and reassembly (SAR), and transmission convergence circuits. These cores give you ready access to building blocks for well defined, standard functions, while providing the ability to customize a portion of the FPGA that is unique to your application.

For example, a flexible ATM Transmission Convergence circuit can be constructed using the UTOPIA Slave, Cell Delineation and Cell Assembler cores, along with some custom logic and a framer. This would be very useful for a manufacturer of ATM Test equipment, who could use a single FPGA and reconfigure it with T1/E1, T3/E3, ATM-25 or ADSL framers, for example, based on the type of system under test.

UTOPIA Slave Core
The UTOPIA Slave core (CC-141f) conforms to the ATM Forum's UTOPIA Level 2 specification and supports 8 and 16 bit operation at 25, 33 and 50 MHz. It includes separate transmit and receive blocks that can be used individually or combined in one FPGA to form a complete UTOPIA transceiver. Both blocks use Xilinx distributed SelectRAM to implement on-chip rate-matching FIFOs.

Cell Delineation Core
The Cell Delineation core (CC-200f) carries out the functions required in the receive stream of the Transmission Convergence sub-layer of an ATM Physical Layer processor. The input is a byte-aligned cell stream containing 53-byte cells with 5 bytes of header and 48 bytes of payload. CC-200f delineates cells as prescribed in ITU specification I.432 and gives out header and payload.

Cell Assembler Core
The Cell Assembler (CC-201f) carries out the functions performed in the receive stream of the Transmission Convergence sub-layer of an ATM Physical Layer processor. The input is a byte-aligned cell stream containing 52-byte cells with 4 bytes of header and 48 bytes of payload. The Cell Assembler computes the Header Error Check (HEC) sequence and inserts it in the fifth byte position of the outgoing stream; thus creating the 53 byte output cell.

CRC10 and CRC32 Cores
The CRC10 (CC-130f) and CRC32 (CC-131f) cores are fully compatible with the ITU-T Recommendation I.363 . These cores are typically used in ATM SAR (AAL3/4, AAL5), ethernet, HDLC and other communication circuits. Each core includes individual generator and verifier modules that can be used individually or combined. The CRC32 core operates at 30 MHz single clock operation, faster than similar cores from competing PLD providers. The CRC10 and CRC32 cores are also support the new Spartan family of low-cost FPGAs.

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More Information

Press Release
UTOPIA Slave Datasheet
Cell Delineation Datasheet
Cell Assembler Datasheet
CRC10 Datasheet
CRC32 Datasheet
CoreEl Microsystems
AllianceCORE Program