Design
- Create a design specification before beginning design
work
- Always use the latest development system and Service
Pack
- Use design components optimized for Xilinx
- Use synchronous design practices
- Use HDL coding that works
well for FPGAs
- Use CASE statements in place of IF-THEN-ELSE
- Design for a lookup table based architecture
- Limitation is on number of inputs, not complexity
- Recognize that inverters are always free
- Consider
one-hot encoding for
state machines
- Consider
LFSRs for counters
- Partition logic intelligently
- Flip-flops at the outputs of the block
- Pipeline logic whenever speed is more important than latency
- Duplicate logic to improve routing delays or logic reduction
- Use built-in resources whenever possible
- Carry logic
- Global initialization
- Dedicated clock buffers
- Dedicated clock enables
- Use RAM in place of flip-flops
- Small state machines
- FIFOs
Implementation
- Do a functional simulation first
- Use realistic timing constraints
to control placement and routing
- On the first implementation try, examine the mapping
results before continuing to place and route
- Verify the correct logic resources are used
- Verify that no logic is incorrectly deleted
- Estimate if the number of levels of logic is sufficient
to meet timing
- On the first place and route try, use the default options
- For the best results, do not pre-assign pin locations
- Use the Timing Analyzer for quick timing analysis before
simulation
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