Answers Database
JTAG - How to configure a XC4000/XC5200/Spartan families via Boundary Scan
Record #940
Product Family: Hardware
Product Line: 4000E
Product Part: 4000E
Problem Title:
JTAG - How to configure a XC4000/XC5200/Spartan families via Boundary Scan
Problem Description:
Urgency: Hot
General Description:
With the exception of the XC3000 family, it is possible to
configure XC4000, Spartan and XC5200 devices via the boundary scan pins
TMS,TCK,TDI, & TDO. This solution applies to the XC4000(including
XC4000EX), Spartan and the XC5200 devices.
NOTE: This solution record is the document on configuring an
XC4000/XC5200/Spartan FPGAs via the JTAG TAP. Information in this
solution record superceeds all other documents on FPGA JTAG
configuration.
Solution 1:
Please refer to XAPP017 for a complete description of JTAG in Xilinx FPGA's:
http://support.xilinx.com/xapp/xapp017.pdf
Solution 2:
PART A
You can Use the Xilinx Alliance 1.5 JTAG Programmer software to
program XC4000, XC5200 and Spartan devices in a JTAG chain. Refer
to the A1.5 JTAG Programmer user guide on more information.
PART B
*NOTE*
To understand part B of this solution, you must have an understanding
of JTAG/Boundary Scan. This solution applies to the XC4000 family
and XC5200 family of devices.
CONFIGURE - Steps to Follow to configure a Xilinx
XC4000, or XC5200 via JTAG:
The bitstream format is identical for all configuration
modes. A user can use a .bit file or a .rbt file, depending on
whether the user wants to read a binary file(.bit) or an ascii
file(.rbt). Express mode bitstreams cannot be used in configuring
via boundary scan.
Xilinx also recommends that the mode pins of the device be tied low
before starting the configuration.
1. Turn `on' the boundary scan circuitry.
This can be done one of three ways, either via powerup
or via a configured device with boundary scan enabled,
or by pulling the /PROGRAM pin low.
If you want to do this via powerup, then just hold the
INIT pin low when power is turned on. When VCC has
reached VCC(min), then the TAP can be toggled to enter
JTAG instructions. The INIT pin can be held low one of
two ways, either manually or with a pulldown. If you
choose to manually hold the INIT low, then the INIT pin
must be held low until the CONFIGURE instruction is
the current instruction. If you choose a pulldown, use a
pulldown which pulls the INIT pin down to approxi-
mately 0.5V. The pulldown has the merit of holding INIT
low whenever the FPGA is powered-up, and letting the
user `see' an attenuated INIT pin during configuration.
After the FPGA has been configured, if you want to
reconfigure a configured device that has boundary scan
enabled after configuration, then just start toggling the
boundary scan TAP pins.
2. Load the Xilinx Configure instruction into the IR.
The Xilinx Configure instruction is 101(I2 I1 I0). I0 is the
bit shifted in first into the IR.
3. After shifting in the Xilinx CONFIGURE instruction,
make the CONFIGURE instruction the current JTAG
instruction by going to the update-IR state. When TCK
goes low in the update-IR state, the FPGA is now in the
JTAG configuration mode and will start clearing the con-
figuration memory; The CONFIGURE instruction is now
the current instruction, which must be followed by a ris-
ing edge on TCK. If you chose to manually hold the INIT
pin low, then the INIT pin must be held low until the
CONFIGURE instruction is the current instruction.
4. Once the Xilinx CONFIGURE instruction has been
made the current instruction, the user must go to the
run-test/idle state, and remain in the run-test/idle state
until the FPGA has finished clearing it's configuration
memory.
The approximate time it takes to clear an FPGA's con-
figuration memory is: 2 * 1 us * (# of frames per device
bitstream).
When the FPGA has finished clearing it's configuration
memory, the open-collector INIT has gone high impedance.
At this point, the user
should advance to the shift-dr state. Once the TAP is in
the shift-dr state and the INIT pin has been released, clocks
on the TCK pin will be considered configuration clocks
for data and length count.
5.
In the shift-DR state, start shifting in the bitstream. Con-
tinue shifting in the bitstream until DONE has gone high
and the startup sequence has finished.
During the time you are shifting in the bitstream via the
TAP, the configuration pins LDC, HDC, INIT, PRO-
GRAM, DOUT, and DONE all function as they normally
do during non-JTAG configuration. These pins can be
probed by the user, or after completion of configuration, or if
configuration failed, the SAMPLE/PRELOAD instruction can be
used to view these IOB's(except PROGRAM or DONE).
LDC is low during configuration. HDC is high during
configuration. INIT will be high impednace during configuration, but
if a CRC error or frame error is detected, INIT will go
low; If a pulldown is present on INIT then the user must
probe INIT with a meter or scope;With a pulldown(as in step 1)
attached to the INIT pin, the user will see a drop from
approximately 0.5V to OV if INIT drops low to indicate a
data error. PROGRAM can still be used to abort the
configuration process. DOUT and TDO will echo TDI
until the preamble and length count are shifted into TDI;
When the preamble and length count have been shifted
into the FPGA, DOUT will remain high. DONE will go
high when configuration is finished. Until configuration
is finished, DONE will remain low.
Some Additional Notes:
(a) It is possible to configure several 4K, and/or 5K
devices in a JTAG chain. But unlike non-JTAG daisy-
chain configuration, this doesn't necessarily mean merging all the
bitstreams into one bitstream. In the case of JTAG con-
figuration of Xilinx devices in a JTAG chain, all devices,
except the one being configured, will be placed in
BYPASS mode. The one device in CONFIGURE will
have its bitstream downloaded to it. After configuring
this device it will be placed in BYPASS, and another
device will be taken out of BYPASS into CONFIGURE.
(b) If you are configuring a 'long' daisy-chain of
JTAG devices(TDI connected to TDO of the previous device),
the bitstream for the device with the CONFIGURE instruction
may need to have its bitstream modified.
For example, lets say that the a user has the following
daisy-chain of devices:
device1---device2-----device3
Device1's TDO pin is connected to device2's TDI pin;
Device2's TDO pin is connected to device3's TDO pin.
The way to configure this chain is to place one
device in CONFIGURE, and the other two in BYPASS. Let's
further assume that device1 and device2 configure in this
way, but device3 never configures. Specifically, device3's
DONE pin never goes high; The problem is the bitstream
length count. A possible cause, aside from bitstream
corruption, is that the final value of the length count
computed by the user/software was reached before
the loading was complete.
There are two solutions. One solution involves just continually
clocking TCK(for about 15 seconds) until DONE goes high. The other
solution is to modify the bitstream;Increase the length count by
the number of devices ahead of the device under configuration.
For example, in the testcase above, the user increase the length
count value by 2. (In a daisy-chain of devices configuring via
boundary scan, devices in BYPASS will supply the extra 1's needed
at the head of the bitstream)
(c) In general for the XC4000 and XC5200, if you are configuring
these devices via JTAG, finish configuring the device first before
executing any other JTAG instructions; Once configuration through
boundary scan is started, the configuration operation must be
finished.
(d) If boundary scan is not included in the design being
configured, then make sure that the release of I/Os is the last
event in the startup sequence.
If boundary scan is not available, the FPGA is configured, and the
I/Os are released before the startup sequence is finished, the
FPGA will not respond to input signals and outputs won't respond
at all.
(e) Re-issuing a boundary scan CONFIGURE instruction after the the
clearing of configuration memory will cancel the configure
instruction.
The proper method of re-issuing a CONFIGURE instruction after the
configuration memory is cleared is to issue another boundary scan
instruction, and then follow it by the CONFIGURE instruction.
(f) If configuration through boundary scan fails, there are only
two boundary scan instructions available: sample/preload and
bypass. If a another reconfiguration wants to be attempted, then
the PROGRAM pin must be pulled low, or the FPGA must be repowered.
(g) When the CONFIGURE instruction is the current instruction,
clocks on the TCK pin are not considered configuration clocks
until the /INIT pin has gone high impedance, and the TAP is in the
shift-dr state.
(h) If the user is attempting to configure a chain of
devices, it is recommended that the user only configure the
chain in all boundary scan mode, or use the non-boundary scan
configuration modes. It is possible to configure a daisy-chain
of devices, some in boundary scan and some in non-boundary scan
configuration. Configuring in a mixed mode will not necessarily
give the user a continuous boundary scan chain, which may or
may not be a problem for a particular user's applications.
(i) When configuring a chain of Xilinx FPGA's via boundary scan,
this doesn't require merging all the bitstreams into one
bitstream, as in non-boundary scan configuration daisy-chains.
When the FPGA is in boudary scan configuration, the same
configuration circuitry used for non-boundary scan configuration
is used. So, if a user would like, it is possible for a user to
merge all bitstreams into one bitstream, using the Prom Formater
or makeprom/promgen. In a case where the user wants to merge the
bitstreams into one bitstream, the user should configure as in
note (a) above. Additionally, the user will have to tie all /INIT
pins together. All DONE pins will also have to be tied together.
(j) A n-bit instruction takes n-1 TCK's to load into a n-bit IR
register. In the IEEE 1149.1 implementation of the tap, a shift
in the IR/DR happens whenever the TAP is in the shift-IR/shift-DR
state, and when leaving the shift-IR/shift-DR state. Based on
this behavior, it takes n-1 TCK's to shift in a n-bit instruction.
In the case of FPGA's from Xilinx that can configure via JTAG, the
user only needs to stay in shift-IR for 2 TCK's to shift in the
3-bit CONFIGURE instruction.
NOTE: The intention of configuration for a daisy-chain was to use
either all the devices in boundary scan, or all the devices in
non-boundary scan configuration.
End of Record #940 - Last Modified: 01/10/00 21:17 |
