Answers Database
A1.4/F1.4 PAR - PAR introduces DRC error: "ERROR:x45dr - netcheck: Signal <net> is routed to the O pin of block <comp> on routing which is not available because the EC pin is using the Logic Ze ro option.
Record #3570
Product Family: Software
Product Line: FPGA Implementation
Product Part: par
Product Version: 1.4.
Problem Title:
A1.4/F1.4 PAR - PAR introduces DRC error: "ERROR:x45dr - netcheck: Signal <net> is routed to
the O pin of block <comp> on routing which is not available because the EC pin is using the Logic
Ze
ro option.
Problem Description:
PAR appears to finish successfully, but DRC flags the following
error introduced during routing:
ERROR:x45dr - netcheck: Signal <net> is routed to the O pin of block <comp> on routing which is not
available because the EC pin is using the Logic Zero option.
Solution 1:
A fix for this routing error is included in the current M1.4 Core
Applications patch available from the Xilinx Download Area:
Solaris: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
SunOS ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
HPUX: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
Win95/NT: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt17.zip
End of Record #3570 - Last Modified: 04/30/99 09:30 | 
