Answers Database
Timing Simulation shows XX's on the outputs of CORE Generator COREs containing ROM and/or R
Record #3663
Product Family: Software
Product Line: Coregen
Product Part: Coregen
Product Version: c1_4
Problem Title:
Timing Simulation shows XX's on the outputs of CORE Generator COREs containing ROM and/or R
Problem Description:
Urgency: hot
General Description:
Outputs of CORE Generator COREs containing ROM and/or RAM may
be XX in simulation.
Solution 1:
X's may be seen on the outputs of CORE Generator modules
containing ROM or RAM when the function generator inputs are
forced to GND or VCC (Constant Coefficient Multipliers, FIR
Filters,for example).
The problem is caused by a bug in the Xilinx Mapper v1.4.
A Patch to the v1.4 Mapper is available on the Xilinx FTP site.
Solaris: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
SunOS ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
HPUX: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
Win95/NT: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt17.zip
End of Record #3663 - Last Modified: 08/18/98 18:15 | 
