Answers Database
A1.4/F1.4 PAR - PAR tries to insert bogus route-thru in clock IOB.
Record #3742
Product Family: Software
Product Line: FPGA Implementation
Product Part: par
Product Version: 1.4.
Problem Title:
A1.4/F1.4 PAR - PAR tries to insert bogus route-thru in clock IOB.
Problem Description:
PAR introduces drc errors by incorrectly trying
to use a used clock IOB site for a route-thru:
Signal REC_DISP/DISPLAY/D_CTRL/D_DRAMAD/RDCLO7 is connected
to O pin and I1 pin of the used clock IOB "CLK4X", but the
route-thru is not connected internally. This leads to DRC
warnings:
WARNING:x4kdr:20 - Blockcheck: "O" on comp (mapped physical
logic cell) "CLK4X" has a signal attatched to the pin, but
the comp is not programmed to use the pin.
WARNING:x4kdr:20 - Blockcheck: "I1" on comp (mapped physical
logic cell) "CLK4X" has a signal attatched to the pin, but
the comp is not programmed to use the pin.
Solution 1:
This problem is fixed in the latest M1.4 Core Tools Patch
available on the Xilinx Download Area:
Solaris: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
SunOS ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
HPUX: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
Win95/NT: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt17.zip
End of Record #3742 - Last Modified: 04/30/99 09:35 | 
