Xilinx Answer #7391 : C_IP2, V2.1i COREGEN: Virtex Variable Parallel Multiplier module "Set Overrides Clear" option behaves the same way as "Clear Overrides Set"

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C_IP2, V2.1i COREGEN: Virtex Variable Parallel Multiplier module "Set Overrides Clear" option behaves the same way as "Clear Overrides Set"

Record #7391
Product Family: Software

Product Line: Coregen

Product Part: Coregen

Product Version: 2.1

Problem Title:

C_IP2, V2.1i COREGEN: Virtex Variable Parallel Multiplier module "Set Overrides Clear" option behaves the same way as "Clear Overrides Set"

Problem Description:
Urgency: standard

General Description:
The Virtex Multiplier core v1_0.1 released in C_IP2 has an option
that allows the user to customize the core so that a Set input will
override a Clear input when both are asserted at the same time.
This option can also be specified in an .XCO file by setting the
set_clear_priority parameter to "set_overrides_clear.

In the 1.0 version of the multiplier, this option does not work. The
result is that Clear overrides Set regardless of what the user
has specified.

Solution 1:

There is no workaround to this problem at this time.

End of Record #7391 - Last Modified: 09/01/99 12:01

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