Answers Database
2.1i COREGEN, C_IP3: MAP: "ERROR:xvkpu - Unable to obey design constraints" / Distributed Memory Cores may fail in MAP
Record #7906
Product Family: Software
Product Line: LogiCore
Product Part: Coregen IP Modules
Problem Title:
2.1i COREGEN, C_IP3: MAP: "ERROR:xvkpu - Unable to obey design constraints" / Distributed
Memory Cores may fail in MAP
Problem Description:
Urgency: hot
General Description:
Some of the configurations of the CORE Generator Single Port and Dual Port
Distributed Memory core released in C_IP3 may fail in MAP when output
registers are used in the module.
The failure is associated with the following MAP error:
"ERROR:xvkpu - Unable to obey design constraints"
The current assessment is that MAP appears to be unable to combine the module
output flip-flops with distributed RAM elements in a single CLB. There also appears to
be some effect due to certain pipeline register configurations.
Solution 1:
Try regenerating the Distributed RAM without requesting registered outputs. The flip-flops can be
generated separately and connected to the RAM modules.
The drawback of this approach is possibly higher CLB utilization and slightly reduced performance
because the RAM and register logic will end up in separate CLBs.
Solution 2:
Try regenerating the memory with the "Create RPM" option deselected.
The drawback of this workaround is a reduction in performance.
Solution 3:
Try changing the number of pipeline levels. In some cases this will allow MAP to succeed.
End of Record #7906 - Last Modified: 10/21/99 14:49 |
