Xilinx Answer #8315 : 2.1i COREGEN, C_IP4: "FATAL: RPM arrangement for a1/RAM_0/BIT_1 cannot be placed in RPM arrangement for a1/RAM_0 due to resource contention." for RAM-Based Shift Register

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2.1i COREGEN, C_IP4: "FATAL: RPM arrangement for a1/RAM_0/BIT_1 cannot be placed in RPM arrangement for a1/RAM_0 due to resource contention." for RAM-Based Shift Register

Record #8315
Product Family: Software

Product Line: LogiCore

Product Part: Coregen IP Modules

Problem Title:

2.1i COREGEN, C_IP4: "FATAL: RPM arrangement for a1/RAM_0/BIT_1 cannot be placed in RPM arrangement for a1/RAM_0 due to resource contention." for RAM-Based Shift Register

Problem Description:
Urgency: standard

General Description:
When generating a RAM-Based Shift Register with the following combination of
options:

    "Create RPM" = true
    "Register Final Bit" = true
    "Clock Enable" = true
    "Sync Controls Override CE" = true
     "synchronous_settings" = anything except "none"
     "asynchronous_settings" = anything except "none"

the core will fail in CORE Generator with the following error message:

FATAL: RPM arrangement for a1/RAM_0/BIT_1 cannot be placed in RPM arrangement for a1/RAM_0 due to re source contention.
ERROR: An internal error has occurred. Please call Xilinx support.
FATAL: Cannot place row template arrangement for a1 because resource assignment is not complete. ERROR: An internal error has occurred. Please call Xilinx support.
WARNING: Core a1 did not generate product ImpNetlist.
Debug: Implementation netlist failed!!
ERROR: Errors encountered while generating a1 (RAM-based_Shift_Register 1.0). No output files have b een generated.

Solution 1:

To work around this problem, try disabling the "Create RPM" option. The drawback is that performance may deteriorate to a certain extent.

End of Record #8315 - Last Modified: 12/21/99 17:46

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