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2.1i COREGEN, VERILOG: 'Error! Too many module instance parameter assignments [in] "XilinxCoreLib/async_fifo_v1_0.v", 839: C_GATE_BIT_V1_0'


Record #8374

Product Family: Software

Product Line: LogiCore

Product Part: Coregen IP Modules

Problem Title:

2.1i COREGEN, VERILOG:  'Error!	Too many module instance parameter assignments [in]
"XilinxCoreLib/async_fifo_v1_0.v", 839: C_GATE_BIT_V1_0'



Problem Description:
Urgency: Standard

General Description:
When compiling Coregen's Asychronous FIFO, the following error may be
seen:

"Too many module instance parameter assignments    [Verilog-TMIPA]
	  "XilinxCoreLib/async_fifo_v1_0.v", 839:
	  C_GATE_BIT_V1_0 #(init_val, yes, yes, 1, no, yes
	  , no, no, no,   yes, no, no, no, 2, "10", 1, "0"
	  , 0, 1)  nand_fd(.I(nand_in), .O(fake_out), .clk(
	  clk), .q(q_out), .CE(vcc), .AINIT(rst), .ASET(
	  fake_in), .ACLR(f..."



Solution 1:

The Asynchronous FIFO Verilog model contains several instantiations of the
C_GATE_BIT_V1_0 module.

The instance starting on line 839 in the FIFO model passes one extra parameter
value (19 total) instead of the 18 required to configure the C_GATE_BIT_V1_0.v
Verilog model. Two lines down from line 837 (the beginning of the declaration)
there is an extra "yes" entry which should be edited out of the model:
C_GATE_BIT_V1_0 #(init_val,
		yes,
		yes,  <--------------------------- extra "yes" parameter entry
		  1,
		  no,
		 yes,
		 no,
		  no,
		  no,
		  yes,
		  no,
		  no,
		  no,
		  2,
		  "10", //c_nand,
		  1,
		 "0",
		 0,
		 1
		 )



Solution 2:

Alternatively, you can generate a post-NGDBUILD gate level simulation netlist following the instructions in (Xilinx Solution #8065).




End of Record #8374 - Last Modified: 02/07/00 09:52

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