Xilinx Virtex Power Estimate Worksheet Version 1.5

Xilinx Virtex Power Estimate Worksheet Version 1.5 (c) Copyright Xilinx Inc 1999, All Rights Reserved.
Design Notes
Target Device	Target Package	Total Estimated Design Power (mW)	Estimated Design VCCint 1.8V Power (mW)	Estimated Design VCCo 3.3V Power (mW)	Estimated Design VCCo 2.5V Power (mW)	Estimated Design VCCo 1.8V Power (mW)	Estimated Design VCCo 1.5V Power (mW)	Estimated Design Output Sink Power (mW)
		36	0	0	0	0	0	0
This worksheet is designed to be used as a pre-implementation tool to estimate a design's power consumption. Actual power consumption must be determined in circuit under the appropriate operating conditions.
User design data should only be entered in the black and white boxes below. For more information on this worksheet please see the License and User Guide
Please send any comments on this worksheet to hotline@xilinx.com marked for the attention of the Virtex Power Estimator Developers.
Note: This worksheet does contain JavaScript functions, but no Java or ActiveX components.
Device Quiescent Power
								VCCint Subtotal (mW)
							Total	36
CLB Logic Power
Name	Frequency (MHz)	Total Number of CLB Slices	Total Number of Flip/Flop or Latches	Total Number of Shift Register LUTs	Total Number of Select RAM LUTs	Average Toggle Rate %	Amount of Routing Used	VCCint Subtotal (mW)
								0
								0
								0
								0
								0
								0
								0
								0
							Total	0
Block SelectRAM Power
Name	Total Number of RAMB4 Cells	Port A Frequency (MHz)	Port A Width	Port A Enabled Rate %	Port B Frequency (MHz)	Port B Width	Port B Enabled Rate %	VCCint Subtotal (mW)
								0
								0
								0
								0
								0
								0
								0
								0
							Total	0
Clock Delay Locked Loop Power
Name	Clock Input Frequency (MHz)	DLL Frequency Type						VCCint Subtotal (mW)
								0
								0
								0
								0
								0
								0
								0
								0
							Total	0
Input/Output Power
Name	Frequency (MHz)	IO Standard Type	Total Number of Inputs	Total Number of Outputs	Average Output Toggle Rate %	Average Output Load (pF)	VCCint Subtotal (mW)	VCCo Subtotal (mW)
							0	0
							0	0
							0	0
							0	0
							0	0
							0	0
							0	0
							0	0
						Total	0	0


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Xilinx Virtex Power Estimate Worksheet Version 1.5 (c) Copyright Xilinx Inc 1999, All Rights Reserved.

Device Quiescent Power

CLB Logic Power

Block SelectRAM Power

Clock Delay Locked Loop Power

Input/Output Power

Xilinx Virtex Power Estimate Worksheet Version 1.5
(c) Copyright Xilinx Inc 1999, All Rights Reserved.