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Frequently Asked Questions - Xilinx 32-Channel ADPCM
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Q1) The core is compliant with G.726, does it cover other standards?
A1) Yes, having compliance with G.726 the core automatically is compatible with G.726a, G.723 and G.721. The core
is not compliant with G.727.
Q2) Can I mix between law and uniform inputs across all the channels?
A2) Yes, in duplex and flexible mode each channel may be individually configured for PCM law and compression ratio.
This should be performed during the CLR processes. In flexible mode each channel requires 4 clock cycles to be
configured, in duplex mode 8 clock cycles per channel are needed.
Q3) Does the core require the use of off-chip RAMs?
A3) No, all the RAM required for the core to operate is incorporated within the on chip Block Ram.
Q4) Do all 32 channels need to be used?
A4) No, 32 is the maximum number of duplex channels (or 64 simplex channels) supported by the core. To use less
channels, only address those channels required for the system.
Q5) Can I switch between 'flexible' and 'duplex' mode on the fly using the MODE input?
A5) No, switching the MODE signal during core operation will cause unpredictable results.
The MODE signal should be set from reset and not change during processing.
Q6) In 'flexible' mode do I have to use all the channels to either compress or expand?
A6) No, each sample can be set individually to compress or expand using the value of EDC
when DSS is asserted high unless the core busy indicator BSY is high.
Q7) How fast must the core operate in order to handle 32 channels?
A7) From the PCM standard samples are entered at 8KHz, the core processes each channel
over 16 cycles per direction per channel=> 8KHz* 16*2 *32 channels = 8.192MHz
clock rate. This is the minimum clock speed required to operate 32 channels. Example
implementations have shown the core to operate well in excess of this speed, this helps guarantee performance when
the core is integrated with other modules.
Q8) What test software was used to verify the core?
A8) The core has been verified using ITU standard test vector sets with ModelTech V5.3d.
The core and testbench have also been verified to operated correctly with VerilogXl
and VCS simulators.
Q9) How do I integrate the core into my design?
A9) Using the template provided (ADPCM32.vho or ADPCM32.veo) instantiate the core
within your system code. Place the core edif netlist in your synthesis directory.
Synthesizing your system code will instantiate the core as a 'black-box' component
in the output edif netlist. Running 'Program Manager' on the output netlist will
incorporate the core netlist into the design automatically.
Q10)What can I do if I require more than 32 duplex ( or 64 simplex ) channels?
A10)We recommend that extra instantiations of the core are utilized to support the required
number of channels up to the limit of the available FPGA resources.
Q11)How do I select between 8-bit logarithmic PCM and the uniform PCM?
A11)The input to each channel can be set to either 8-bit logarithmic PCM and uniform PCM on a sample to sample
basis using the PCM input signal.
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