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Frequently Asked Questions - Xilinx Single-Channel HDLC
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Q1) Do I need to use off-chip RAM with the HDLC1 core?
A1) No, all the RAM required by the core has been integrated in on-chip RAM.
Q2) How do I integrate the core into my system design?
A2) Using the template provided (HDLC1.vho or HDLC1.veo) instantiate the
core within your system code. Place the core edif netlist in your
synthesis directory. Synthesizing your system code will instantiate the
core as a 'black-box' component in the output edif netlist. Running
'Program Manager' on the output netlist will incorporate the core netlist
into the design automatically.
Q3) Is the LogiCore HDLC bit stuffed or Byte stuffed?
A3) The LogiCore HDLC controller is bit stuffed. Between frame flags,
sequences of five numerical ones will have an extra zero automatically inserted (Tx) or
removed (Rx).
Q4) Is the core fully synchronous?
A4) The core is synchronized to the PCM highway clock, i.e. the core is
synchronous with the serial data bit rate.
Q5) Can I instantiate more than one HDLC1 core for higher channel counts?
A5) Yes - Use the TxEN and RxEN signals to stall the non-selected HDLC1
Core. An external mux is necessary to select which of the TxD signals
drives the serial bus. For more than 8 channels the LogiCore HDLC32
core is recommended.
Q6) How do I send a frame?
A6) Configure the channel's Address register and enable the HDLC protocol.
Drive the data for the first data byte of the frame on TxFrameData
along with TxFrameStart. Once TxDataStrobe is asserted on a tick when
the channel is selected, the frame will have started. Drive the next
data byte on TxFrameData until TxDataStrobe is seen again, and so on.
For the last byte assert TxFrameEnd at the same time as driving the last
data byte.
Q7) What's the limit on frame size (MTU)?
A7) There is no limit in the HDLC core. The data part of a frame can be any size.
Q8) How are corrupted frames indicated?
A8) The receiver asserts RxFrameEnd, RxDataStrobe and the last data byte on
RxDataOut at the end of every frame. If the FCS field indicates the frame
was corrupted during transmission, then RxFrameError is also asserted at
this time.
Q9) How can I select between transmitting the Idle sequence and empty frames
when I have no data to send?
A9) The HDLC core will only transmit idle sequence (all ones) when the HDLC
protocol is disabled in the Tx Control Register. If HDLC is enabled, then
back to back flags (empty frames) will be sent in the absence of any
data. The receiver core can handle either type of inter frame fill.
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