For Immediate Release SAN JOSE, Calif., October 27, 1997 -- Xilinx, Inc., (NASDAQ:XLNX), the world leader in programmable logic solutions, announced today the extension of the popular XC4000X FPGA family delivering densities up to 500,000 system gates* (20,000 logic cells). The new Xilinx XC4000XV family initially has four devices, offers system performance of over 100 MHz, and features 2.5-volt internal operation with 3.3-volt I/Os to allow optimum performance and compatibility with existing voltage standards. This family is the first with five metal layers. "We announced our five-year roadmap last January, which clearly defined our plans to provide higher density FPGA families on advanced processes. In the course of six months, we have delivered ten members of the XC4000XL family of high-density and high-performance FPGAs. These are widely accepted by customers as leaders in density and performance," said Wim Roelandts, Xilinx chief executive officer. "With our migration to 0.25 micron process, the XC4000XV FPGA family represents our next leadership step to bring the benefits of FPGA reconfigurability and time-to-market advantages to traditional ASIC users who demand high-performance and high-density logic." Delivering ASIC performance and density Digital designers are now considering incorporating the time-to-market benefits that Xilinx high-density, high-performance FPGAs have for their designs that were traditionally filled with custom solutions. According to Jordan Selburn, principal analyst at Dataquest, the Xilinx XC4000XV family of FPGAs, in conjunction with HardWire arrays, can address approximately 45 percent of the 1997 gate-array design starts based on the XC4000XV maximum performance and density levels. In customers’ hands now "Our customers are demanding several million gates of programmable logic in our most advanced product, the System Explorer. By using the XC40125XV, the highest density programmable logic device available today, we are able to achieve these density levels," said Vincent Coli, director, product marketing at Aptix the leader in reconfigurable system prototyping solutions. We use Xilinx for their density because it's here today." Architectural advantages of the XC4000X series The XC4000XV family is an advanced implementation of the XC4000EX/XL architecture with Xilinx segmented routing and distributed RAM. These features make an ideal platform for implementing cores. Local routing resources in short, segmented routing allow for predictable performance regardless of how much logic is employed and how large the device is. With non-segmented interconnect architectures, cores will slow down unpredictably as surrounding logic is added or as larger devices are required. Performance predictability is a requirement for designs with intellectual property because designers choose cores independently of device density and expect performance to remain the same as the design evolves. Further, due to footprint-compatibility advantages, current XC4000XL customers can easily and immediately upgrade to the higher-density XC4000XV products. Xilinx leadership in digital design Xilinx software solutions enable users to achieve up to 100 percent utilization with a push-button flow. HDL-based EDA partners are able to provide optimum performance by working closely with Xilinx on algorithms to map directly into the specific features of the architecture. Powerful "auto-interactive" tools allow the flexibility to check the design at all points through the flow, plus the ability to go beyond the barriers normally present in a push-button only flow. SMARTspecs software is the industry’s most robust timing constraint language and is especially important for large designs to ensure that multi-cycle and false paths can be accounted for during implementation. Current design tools from Xilinx EDA Alliance partners that support the XC4000XV family. These partners have libraries available now. Xilinx Foundation Software series, widely distributed in November, will also support the XC4000XV family. Price and availability Samples of the XC40125XV device on 0.25-micron process are available.
Initial pricing for the family starts at $1500 in 100-piece quantities
for the XC40125XV-2 in the ball grid array (BGA) package. HardWire pricing
for the same device will be between $60 - $100. All the devices will be
available in the BG560 and the PG559 packages.
Founded in 1984, Xilinx is the world’s largest supplier of programmable logic solutions producing industry-leading device architectures and world class design software. Headquartered in San Jose, Calif., the company pioneered the market for field programmable gate array (FPGA) semiconductor devices that provide high integration and quick time-to market for electronic equipment manufacturers in the computer, peripheral, telecommunications, networking, industrial control, instrumentation, consumer, and high reliability/military markets. For more information on Xilinx, access the World Wide Web site at www.xilinx.com. * Assuming 30 percent configurable logic blocks (CLBs) used as RAM Xilinx is a registered trademark of Xilinx, Inc. HardWire,
Foundation, SMARTspecs and all XC-prefix products referenced above are
trademarks of Xilinx, Inc. Other brand or product names are trademarks
or registered trademarks of their respective owners.
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